Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-10-19
2003-05-20
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S158000, C711S167000
Reexamination Certificate
active
06567886
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a disk drive apparatus used in a hard disk drive (HDD), etc., and control method therefor, and relates in particular to a disk drive apparatus for high-speed data transfer in a multi-drive environment, and control method therefor.
2. Description of the Related Art
In order to increase access speed, a hard disk drive (HDD) used as an auxiliary storage device for information processing equipment is generally provided with cache memory that temporarily holds data supplied from the information processing equipment (referred to below as the host), or that temporarily holds data read from the magnetic disk until it is transferred to the host, and a controller that performs cache control.
When write data is supplied from the host, the controller holds the supplied write data in the cache memory, then releases the host from write processing. In parallel with this, the controller performs write-system control in which the write data held in the cache memory is sequentially written to the magnetic disk (referred to below as the medium). Also, when there is a read request from the host, the controller instructs the read system to read the expected data from the medium, and holds the data that is read in the cache memory. Then, when there is a read request from the host, if the data to be read is held in the cache memory, it is supplied to the host. By performing this kind of cache control, the apparent access speed of the HDD is increased.
In the small HDDs of recent years, the trend is to use a technique for minimizing the intervention of the HDD's microprocessor (referred to below as the local MPU) in host interface peripheral processing as a means of improving performance by decreasing command overhead, and using hardware implementation of this processing by the host interface controller (HIC) as much as possible.
One possible technique of this kind is the use of a system in which data transfer between the host and cache memory can be performed under HIC control without local MPU intervention, while data transfer between the medium and cache memory requires intervention by the local MPU, which performs data transfer by controlling the hard disk controller (HDC).
The operation for writing data to the medium by means of a write command from the host in this kind of system will be described below.
(1) Once data from the host enters the cache memory via the HIC, the HIC informs the local MPU that a command has arrived from the host. On receiving this information, the local MPU issues an instruction to the HDC to write data in the cache memory to the medium. In response to this instruction, the HDC transfers cache memory data to the medium, and the data is written to the medium.
(2) After this, the HIC issues a notification to the local MPU indicating that transfer to the cache memory from the host has finished, and the HDC issues a notification indicating that writing to the medium has finished.
The operation of the HIC and the local MPU will now be described in greater detail. When the HIC receives a command from the host, it immediately starts data transfer to the cache memory without the intervention of the local MPU, and notifies the local MPU. When this data transfer ends, and as soon as there is space (for example, one block) allowing the next write command to be received in the cache memory, the HIC notifies the local MPU of the end of the command. This notification is to enable the next write command to be latched in the cache memory as soon as it arrives, and is an IDE (Integrated Device Electronics) interface specification.
In this kind of operation, when there is enough space in the cache memory, the HIC independently gives the host an end notification without regard to write processing operations by the local MPU, accepts the next write command from the host, and performs data transfer based on the next write command. Latching as many write commands as possible in the cache memory in this way enables performance to be further improved. In order to perform the above operations, a command queue is provided in the cache memory to hold the various kinds of cache memory commands.
FIG. 9
is a drawing showing the structure of the cache memory command queue. In
FIG. 9
, Q=1, 2, . . . , n are queue addresses, and A, B, C, D, . . . , N are commands held in the cache memory. As shown in
FIG. 9
, commands cached in the cache memory are written in the command queue as A, B, . . . , in order, starting with the oldest command. Queue addresses increase each time a command is accepted, and decrease when the old commands are executed sequentially. Command queue management is performed by the HIC, and the local MPU can take in queue address commands.
Write commands held in the command queue are executed by the HDC in response to a write directive from the local MPU to the HDC, and are written to the medium. Data read from the medium is transferred to the cache memory by the HDC, and then transferred to the host by the HIC.
The disk drive apparatus is provided with memory called a sector buffer, and in order to speed up sequential reads, even though an area read requested by one read command ends, the following area read is proceeded with (“look-ahead”). Thus, in the case of sequential reads, data is already present in the cache memory when the next read command arrives, enabling higher speed to be achieved. The serial number assigned to a usable sector is called the LBA (logical block address).
Also, a hard disk apparatus generally has a “reorder” function that rearranges the execution order of queued commands in order to minimize read/write head movement. The hard disk apparatus places commands received from the host in a queue, and changes the command execution order so that this command list is executed most efficiently and speedily on the logical unit.
That is to say, when data read/writes for multiple sectors are issued to the hard disk apparatus from the host, if sectors were read in the order in which the commands are issued, the head would make numerous two-way moves on the disk, which would be time consuming. Therefore, the order of the commands is changed so as to read/write the sectors according to a schedule that minimizes the amount of head movement. In this case, a schedule is established that takes account not only of the amount of head movement, but also of disk latency and head switching time. The schedule that decides this command order is determined by RPO (rotational position optimization).
FIG. 10
is a block diagram showing the configuration of a hard disk apparatus including the software (microprogram) that implements the above described command processing.
In
FIG. 10
, reference numeral
1
denotes the host interface controller (HIC); reference numeral
2
denotes a drive apparatus that controls HDD drive operations, including control of the voice coil motor (VCM) that drives the actuator mechanism and of the hard disk controller (HDC); reference numeral
3
denotes the interface event handler (I/F event handler); reference numeral
4
denotes the queue handler; reference numeral
5
denotes the command handler (Cmd handler); and reference numeral
6
denotes the drive event handler.
The HIC
1
and the drive apparatus
2
are configured by means of hardware. The interface event handler
3
, queue handler
4
, command handler
5
, and drive event handler
6
are control routines that have functions determined by the microprogram, and are executed by the MPU.
The interface event handler
3
processes events from the HIC
1
, and conveys those events to the queue handler
4
or command handler
5
. When the HIC
1
receives a command, it stores it in a queue area.
When a number of commands are stored in the queue area, the queue handler
4
performs reordering so that the command list is executed most efficiently and speedily, and determines the command to be executed by the command handler
5
. Thereafter, the queue handler
4
requests the command handler
5
to execute the de
Fukuhisa Ryoji
Inoue Kazunori
Saitoh Hirofumi
Bataille Pierre-Michel
Kim Matthew
Raissinia Abdy
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