Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2005-04-22
2008-12-02
Ellis, Kevin (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C360S069000
Reexamination Certificate
active
07461219
ABSTRACT:
Embodiments of the invention ensure both a realtime nature of a realtime processing and data integrity of a non-realtime processing and perform the both processings efficiently when the realtime processing and the non-realtime processing are performed simultaneously. In one embodiment, a time limit is set not only for a realtime processing command but also for a non-realtime processing command and, if the execution of the non-realtime processing command is not completed within the set time limit, the execution of the non-realtime processing command is interrupted forcibly and a host is informed of a data transfer status at the time of the interruption so that the host can restart the interrupted processing based on the data transfer status of the interrupted processing when a time that can be allocated for the non-realtime processing command occurs again.
REFERENCES:
patent: 5787482 (1998-07-01), Chen et al.
patent: 6553476 (2003-04-01), Ayaki et al.
patent: 2006/0253675 (2006-11-01), Johannes Bloks
patent: 10-222310 (1998-08-01), None
Hiratsuka Yukie
Inagaki Yukihide
Uemura Tetsuya
Ellis Kevin
Farrokh Hashem
Hitachi Global Storage Technologies - Netherlands B.V.
Nader Rambod
Townsend and Townsend / and Crew LLP
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