Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-07-31
1998-07-28
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711112, 711129, 711133, 711159, 711170, 348 7, G06F 1212, H04N 710
Patent
active
057874727
ABSTRACT:
A system and method for caching sequential data streams in a cache storage device. For each information stream, a determination is made as to whether its data blocks should discarded from cache as they are read by a consuming process. Responsive to a determination that the data blocks of a stream should be discarded from the cache are read by the consuming process, the data blocks associated with that stream are cached in accordance with an interval caching algorithm. Alternatively, responsive to a determination that the data blocks of a stream should not be discarded from the cache storage device as they are read by the consuming process, the data blocks of that stream are cached in accordance with a segment caching algorithm.
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Dan Asit
Sitaram Dinkar
Chan Eddie P.
Dougherty Anne Vachon
IBM Corporation
Jordan Kevin M.
Kim Hong C.
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