Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2007-11-06
2007-11-06
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S113000, C711S003000, C711S217000, C711S220000, C711S203000, C714S768000
Reexamination Certificate
active
10959982
ABSTRACT:
To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.
REFERENCES:
patent: 5787460 (1998-07-01), Yashiro et al.
patent: 6606715 (2003-08-01), Kikuchi
patent: 2005/0055522 (2005-03-01), Yagi
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Baba Hidemi
Matsunami Naoto
Nishimoto Akira
Sato Masahiko
Bragdon Reginald
Hitachi , Ltd.
Wang Victor W.
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