Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
2005-02-01
2005-02-01
Perveen, Rehana (Department: 2116)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S039000, C710S110000, C710S305000, C710S316000, C711S114000, C711S147000, C711S148000
Reexamination Certificate
active
06850998
ABSTRACT:
In a disk array system of the present invention, each host or disk interface unit is connected to each shared memory unit through a switch unit. The switch unit includes the number of packet buffers greater than the number of the host or disk interface units connected thereto, and can always hold the number of access requests greater than the number of the host or disk interface units. The disk array system uses the packet buffers to compensate for a transfer rate difference between the host interface units and the shared memory units, thereby allowing connection of the host interface units having different performance. The disk array system improves the efficiency of usage of internal paths without increasing the number of I/O ports of the switch unit. The system throughput is thereby improved, and the support for host I/Fs having different performance is thereby facilitated.
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Fujimoto Kazuhisa
Inoue Mitsuru
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Perveen Rehana
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