Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Patent
1995-10-13
1998-04-07
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
39518204, 364DIG1, G06F 1216
Patent
active
057377448
ABSTRACT:
Circuitry for performing hardware assisted XOR operations to generate parity bits for a disk array system. The circuitry includes a controller that acts as an interface between a PCI bus and a DRAM that includes a write-posting cache portion and an XOR buffer portion. The DRAM has a maximum data storage capacity, and the controller is allocated an address space that is twice the maximum storage capacity of the DRAM. The address space is divided into two portions, a normal address range and an XOR address range. A write to the normal address range produces a normal write cycle to the DRAM, while a write to the XOR address range generates a read-modify-write XOR cycle to the DRAM. In the read-modify-write XOR cycles, the read data are XORed with the write data. Selected data are cumulatively XORed to generate new parity information.
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David A. Patterson, et al., "A Case for Redundant Arrays of Inexpensive Disks (RAID), Report No. UCB/CSD 87/391, Dec. 1987.
Callison Ryan A.
Chard Gary F.
Compaq Computer Corporation
Langjahr David C.
Swann Tod R.
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