Disk array controller comprising a plurality of disk array...

Details Disk array controller comprising a plurality of disk array... Disk array controller comprising a plurality of disk array...

2005-04-19

2005-04-19

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S111000, C711S112000, C711S113000

Reexamination Certificate

active

06883064

ABSTRACT:
“Disk array system is presented wherein the plurality of disk array controlling units operate as the sole disk array controller so as to restrain the performance of the cache memory sections of the respective disk array controlling units from deteriorating owing to their physical packaging locations and to maximize the performance thereof in proportion to the number of the controlling units in use. Disk array controller is provided, which controller comprises a host switch interface section, the plurality of respective disk array controlling units provided with a channel interface section, a disc interface section and a cache memory section and a mutual connection network in connection with the channel interface sections, the disk interface sections and the cache memory sections of the respective disk array controlling units. Access performance to the cache memory sections that are dispersedly disposed between the respective disk array controlling units improves so as to enhance the performance of the disk array controller in proportion to the number of the disk array controlling units in use.”

REFERENCES:
patent: 5937428 (1999-08-01), Jantz
patent: 20020054567 (2002-05-01), Fan
patent: 20020188804 (2002-12-01), Rakvic et al.
patent: 1132805 (2001-09-01), None
patent: 11296313 (1999-10-01), None

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