Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2002-03-19
2004-01-27
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S004000, C711S003000, C711S112000, C710S316000, C710S305000, C710S031000
Reexamination Certificate
active
06684295
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to control devices of disk array devices for storing data in a plurality of magnetic disk devices.
2. Description of the Related Art
In view of the fact that the input/output (I/O) performance or throughput of a disk subsystem (referred to as “subsystem” hereinafter) is less by approximately three to four orders of magnitude than the I/O throughput of main memories of computers with semiconductor memory devices as their storage media, attempts have conventionally been made to reduce this difference. Namely, attempts have been made to improve the I/O throughput of the subsystem. One prior known approach to improving the subsystem's I/O throughput is to use a system, called “disk array,” for constituting the subsystem from a plurality of magnetic disk devices such as fixed or “hard” disk drives (HDD5) adaptable for use in storing data in such plurality of HDDs.
FIG. 2
shows an arrangement of one prior art disk array. This includes a plurality of channel interface (IF) units
11
for execution of data transmission between a host computer
50
and a disk array control device
2
, a plurality of disk IF units
12
for execution of data transfer between HDDs
20
and the disk array control unit
2
, a cache memory unit
14
for temporality storing data of HDDs
20
, and a shared memory unit
15
for storing control information as to the disk array controller
2
(for example, information concerning data transfer control between the channel and disk IF units
11
,
12
and the cache memory unit
14
), wherein the cache memory unit
14
and shared memory unit
15
are arranged so that these are accessible from all of the channel IF units
11
and disk IF units
12
. With this disk array, the channel and disk IF units
11
and disk IF units
12
are connected to the shared memory unit
15
on a one-to-one basis; similarly, the channel IF units
11
and disk IF units
12
are connected one by one to the cache memory unit
14
. This connection form is called the star connection.
The channel IF unit
11
has an interface for connection with the host computer
50
and also a microprocessor (not shown) for controlling input/output with respect to the host computer
50
. The disk IF unit
12
has an interface for connection to the HDDs
20
and a microprocessor (not shown) for controlling input/output relative to HDDs
20
. The disk IF units
12
also executes RAID functions.
FIG. 3
shows a configuration of another prior art disk array. It includes a plurality of channel IF units
11
for execution of data transfer between a host computer
50
and a disk array controller
3
, a plurality of disk IF units
12
for execution of data transfer between HDDs
20
and the disk array controller
3
, a cache memory unit
14
for temporality storing data of HDDs
20
, and a shared memory unit
15
for storing control information as to the disk array controller
3
(e.g. information concerning data transfer control between the channel and disk IF units
11
,
12
and the cache memory unit
14
), wherein each of channel IF units
11
and disk IF units
12
is connected by a shared bus
130
to the shared memory unit
15
whereas each channel and disk IF unit
11
,
12
is connected by a shared bus
131
to the cache memory unit
14
. Such connection form is called the shared bus connection.
To render scalable the disk array's architectures, it is required that the disk IF units be additionally provided in accordance with the required number of disks being connected to the disk control device while increasingly providing the channel IF units within the disk array controller as per the required number of channels associated with a host computer(s). However, with the disk array controller of the shared bus connection form shown in
FIG. 3
, because it is impossible to change or modify the transfer ability of the once-mounted shared bus in accordance with the add-in provision of the channel IF units and disk IF units, it remains difficult to flexibly accommodate such add-in extended reconfiguration of the channel IF units and disk IF units.
With the shared bus connection form shown in
FIG. 3
, in the case of employing high-performance processors as the microprocessors provided in the channel IF units and those in the disk IF units, the shared bus's transfer ability becomes a bottle neck when compared to the performance of these processors, which leads to difficulty in keeping up with the growth of high-speed computer processor technology.
Further, in the shared bus connection form shown in
FIG. 3
, in cases where disturbance or operation failures occur at any one of the plurality of channel IF units (or a plurality of disk IF units) as connected to the shared bus, it is difficult to specify which one of the channel IF units (or, disk IF units) suffers from such trouble.
On the contrary, in the disk array controller of the star connection form shown in
FIG. 2
, it is possible to increase the internal path performance or throughput in a way proportional to the number of access paths being connected to either the shared memory unit or cache memory unit, which in turn makes it possible to increase the throughput of internal paths in accordance with the add-in reconfiguration of the channel and disk IF units or alternatively with the performance of processors used. In addition, as the one-to-one (star) connection is used between the channel IF and disk IF units and the cache memory unit or between the channel and disk IF units and the shared memory unit, it is easy to specify a channel IF unit (or disk IF unit) at which an operation failure was occurred.
In the disk array controller of the star connection form, increasing the number of those channel IF units or disk IF units as built therein would result in an increase in number of access paths between the channel and disk IF units and the cache memory unit and between the channel and disk IF units and the shared memory unit. Additionally, the throughput called for disk array control devices tends to further increase due to employment of high-speed channels, such as fiber channel, for connection between host computers and disk array controllers; in order to satisfy this need for improvement of throughput, it should be required to increase the number of access paths between the channel and disk IF units and the cache memory unit and between the former and the shared memory unit to thereby improve the internal path throughput.
However, the data amount of a single data segment or datum to be stored in the cache memory is much greater than the data amount of a single control information item being stored in the shared memory. One example is that in a disk control device as connected to a mainframe, a single datum being stored in the cache memory is several kilobytes (KB) or more or less (for example, 2 KB) whereas one control information item stored in the shared memory is several bytes or therearound (e.g. 4 bytes). Another example is that in disk control devices as connected to host computers of open architectures, a single datum as stored in the cache memory is several tens of byte (e.g. 64 bytes) whereas a single control information item stored in the shared memory is about several bytes (e.g. 4 bytes). Accordingly, the amount of data to be transferred between the channel and disk IF units and the cache memory unit is extremely greater than the data mount being transferred between the channel and disk IF units and the shared memory unit, which leads to a need for letting the data width of an access path between the channel and disk IF units and the cache memory unit be wider than the data width of an access path between the channel and disk IF units and the shared memory unit. For instance, the access path of the former is constituted from a 16-bit width bus whereas the latter is from a 4-bit width bus. For this reason, increasing the line number of access paths between the channel and disk IF units and the cache memory unit would result in creation of a prob
Fujibayashi Akira
Fujimoto Kazuhisa
Kanai Hiroki
Minowa Nobuyuki
Tanaka Atsushi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Peikari B. James
LandOfFree
Disk array control device with two different internal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Disk array control device with two different internal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Disk array control device with two different internal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3210294