Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2011-02-15
2011-02-15
Patel, Hetul (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
Reexamination Certificate
active
07890698
ABSTRACT:
A disk array apparatus improves scalability, performance such as data transfer between different kinds of I/Fs, and maintainability and reliability about boards/PKs configuring the DKC and about a DKC configuration obtained by interconnecting them. The DKC in the disk array apparatus is configured by interconnecting mix PKs each including a base PK and a functional PK which is hierarchically connected to the base PK and on which individually separate functions are mounted. The base PK coexists with and is connectable to a plurality of different I/F-PKs, and includes an intra-package interconnection network for communicating between the functional PKs and with the DKC, and further has a processor interconnection network. The DKC performs a data transfer processing by using the functional PK and the base PK.
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Office Action in JP 2005-062097, dated Jun. 22, 2010 (2 pages), [in Japanese].
Kakihara Shinobu
Mori Kenji
Antonelli, Terry Stout & Kraus, LLP.
Hitachi , Ltd.
Patel Hetul
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