Discrete phase locked loop

Details Discrete phase locked loop Discrete phase locked loop

1996-12-13

2000-06-27

Tse, Young T.

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375327, 455502, 455260, H04L 700

Patent

active

06081571&

ABSTRACT:
A discrete phase-locked loop and method for supporting global synchronization of data communications in a mobile communications system is disclosed. In order to provide for air frame synchronization, air frame data clocks and a synchronization signal must be phase locked to a global time reference signal. This is accomplished through a fully discrete phase lock loop in ASIC or software wherein a state machine is clocked by a high frequency, high accuracy, fixed frequency source already available in the radio terminal equipment. The state machine generates the required air frame data clocks and synchronization signals by completing a counter cycle. At regular intervals, this counter can skip, or double step, for one count to adjust the output phase closer to the phase of the reference signal. The interval for which this correction is maintained is settable by an interval counter. This implementation mimics an elliptic low pass filter.

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T. Kurita et al., "A Digital Phase-Locked Loop with AND Filter", Transactions of the Institute of Electronics and Communication Engineers of Japan Section E, vol. 63, No. 5, pp. 367-368 (May 1980).

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