Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-05-10
2005-05-10
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S758000
Reexamination Certificate
active
06892339
ABSTRACT:
The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP106) and a general purpose host central processing unit (CPU102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108and110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG.4) are used.
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Gusler Lee T.
Polk, Jr. Charles E.
Quirk Patrick J.
Wilson, Jr. Joe L.
Zuckerman Ronald M.
Chaudry Mujtaba
De'cady Albert
Freescale Semiconductor Inc.
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