Electronic digital logic circuitry – Reliability – Fail-safe
Reexamination Certificate
2007-05-01
2007-05-01
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Reliability
Fail-safe
C326S009000, C326S015000, C326S016000
Reexamination Certificate
active
10900312
ABSTRACT:
Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal. Thereby, if a second D-flip-flop circuit F2anegates an output signal [CD], it is able to judge that disconnection or short occurs.
REFERENCES:
patent: 6650149 (2003-11-01), Wong
patent: 3-222552 (1991-10-01), None
patent: 6-85717 (1994-03-01), None
patent: 2003-143239 (2000-05-01), None
Fujino Yasuhiro
Ishibashi Atsuhiko
Renesas Technology Corp.
Tran Anh Q.
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