Disabling sense amplifier

Static information storage and retrieval – Read/write circuit – Differential sensing

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Details

36518905, 365190, 36518902, 327 51, G11C 702

Patent

active

053771508

ABSTRACT:
A memory system that includes a memory array having at least two pairs of data lines, first and second data lines that correspond to columns in the memory array. The memory array also includes two disabling sense amplifier circuits, a first disabling sense amplifier circuit connected to the first data lines and a disabling sense amplifier circuit connected to the second data lines, wherein the disabling sense amplifier circuits produce output signals and may be enabled and disabled. A selection signal is provided for selectively enabling and disabling the disabling sense amplifier circuits, wherein one pair of data lines may be selected. An amplification circuit connected to the disabling sense amplifier circuits provides for amplifying the output signals from the disabling sense amplifier circuits.

REFERENCES:
patent: 4716550 (1987-12-01), Flannagan et al.
patent: 4843264 (1989-06-01), Galbraith
patent: 4891792 (1990-01-01), Hanamura et al.
patent: 5068830 (1991-11-01), Plants et al.
patent: 5099452 (1992-03-01), Yamakoshi et al.

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