Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-12-05
2000-06-20
Nguyen, Hiep T.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711120, 711143, 711142, 711128, G06F 1208
Patent
active
060789921
ABSTRACT:
A technique for providing a dirty line cache to supplement a cache memory, in order to improve caching performance for a processor in a computer system. A fully-associative cache memory is coupled to operate with a main cache memory at a particular level of the cache hierarchy. The supplemental cache is termed as a dirty line cache, since it only stores dirty cache lines. In the preferred embodiment, the dirty line cache is implemented in a write-out buffer of a write-back or write-through cache.
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Intel Corporation
Nguyen Hiep T.
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