Directory-based, shared-memory, scaleable multiprocessor compute

Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data transfer regulating

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

709213, 709230, 709212, 711121, 711130, 711148, G06F 1208, G06F 1516

Patent

active

061416924

ABSTRACT:
A method and apparatus are provided which eliminate the need for an active traffic flow control protocol to manage request transaction flow between the nodes of a directory-based, scaleable, shared-memory, multi-processor computer system. This is accomplished by determining the maximum number of requests that any node can receive at any given time, providing an input buffer at each node which can store at least the maximum number of requests that any node can receive at any given time and transferring stored requests from the buffer as the node completes requests in process and is able to process additional incoming requests. As each node may have only a certain finite number of pending requests, this is the maximum number of requests that can be received by a node acting in slave capacity from any another node acting in requester capacity. In addition, each node may also issue requests that must be processed within that node. Therefore, the input buffer must be sized to accommodate not only external requests, but internal ones as well. Thus, the buffer must be able to store at least the maximum number of transaction requests that may be pending at any node, multiplied by the number of nodes present in the system.

REFERENCES:
patent: 4794521 (1988-12-01), Zeigler et al.
patent: 5274782 (1993-12-01), Chalasani et al.
patent: 5333296 (1994-07-01), Bouchard et al.
patent: 5394555 (1995-02-01), Hunter et al.
patent: 5613071 (1997-03-01), Rankin et al.
patent: 5617537 (1997-04-01), Yamanda et al.
patent: 5675796 (1997-10-01), Hodges et al.
patent: 5680482 (1997-10-01), Liu et al.
patent: 5710907 (1998-01-01), Hagerston et al.
patent: 5740353 (1998-04-01), Kreulen et al.
patent: 5852718 (1998-12-01), van Loo
patent: 5854906 (1998-12-01), van Loo
Anonymous. "Combining Multiple Shared-Buffer Packet Switching Modules to Improve Switch Buffer Capacity", Internat'l Business Machines Technical Disclosure Bulletin, v. 36, n. 11, pp. 545-8, Jan. 1993.
Hwang, Kai. Advanced Computer Architecture: Parallelism, Scalability, Programmability. New York: McGraw-Hill, Inc. 1993.
Akhilesh Kumar et al., Efficient and Scalable Cache Coherence Schemes for Shared Memory Hypercube Multiprocessors, IEEE, Nov. 14, 1994, pp. 498-507.
Jeffrey Kuskin et al., The Stanford FLASH Multiprocessor, IEEE, Apr. 22, 1994, pp. 302-13.
Shubhendu S. Mukherjee et al., Coherent Network Interfaces for Fine-Grain Communication, ISCA, May 1996, pp. 247-58.
Matthias A. Blumrich et al., Virtual Memory Mapped Network Interface for the SHRIMP Multicomputer, IEEE, Apr. 18, 1994, pp. 142-53.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Directory-based, shared-memory, scaleable multiprocessor compute does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Directory-based, shared-memory, scaleable multiprocessor compute, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Directory-based, shared-memory, scaleable multiprocessor compute will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2064989

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.