Directory-based data transfer protocol for multiprocessor...

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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Reexamination Certificate

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07404045

ABSTRACT:
A system for maintaining data coherency in a multiprocessor system includes a first processor having a cache and a directory, a second processor having a directory, and at least one additional processor having a directory and separate from the first and second processors. The first processor is configured to determine if a data line is not found in the cache of the first processor and forward a request for the data line to the second processor. The second processor is configured to forward the data line from the second processor to the first processor, update the directory of the second processor to reflect the data line being forwarded to the first processor, and forward a directory update message to the at least one additional processor to reflect the data line being forwarded to the first processor. An entry in the directories includes a memory address, a most recent data holder, and a line state.

REFERENCES:
patent: 6052762 (2000-04-01), Arimilli et al.
patent: 6078997 (2000-06-01), Young et al.
patent: 6760786 (2004-07-01), Hagersten
Grahn, Hakan, et al;Efficient Strategies for Software-Only Directory Protocols in Shared-Memory Multiprocessors; ISCA 1994, Santa Margherita Ligure, Italy; pp. 38-47.
Lenoski, Daniel, et al;The DASH Prototype: Implementation and Performance; Retrospective, 1995, pp. 80-82.

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