Direct processor cache access within a system having a...

Details Direct processor cache access within a system having a... Direct processor cache access within a system having a...

2007-01-02

2007-01-02

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S118000, C711S146000

Reexamination Certificate

active

10882509

ABSTRACT:
A computer system has a plurality of processors in a multiprocessor system with each processor associated with a cache memory. The cache traffic is monitored by the respective processors to determine the load for each of the cache memories. Signals corresponding to the cache loads are generated and analyzed. A target processor is selected for a push data operation from a bus agent to the cache memory using the load information. The push operations to the caches are optimized based on the cache traffic information.

REFERENCES:
patent: 2002/0194434 (2002-12-01), Kurasugi
patent: 2004/0128450 (2004-07-01), Edirisooriya et al.
patent: 2005/0262235 (2005-11-01), Childress et al.

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