Semiconductor device manufacturing: process – Forming schottky junction – Using refractory group metal
Reexamination Certificate
2002-02-06
2004-06-15
Nguyen, Thanh (Department: 2813)
Semiconductor device manufacturing: process
Forming schottky junction
Using refractory group metal
C438S514000, C438S592000, C438S649000, C438S651000, C438S655000, C438S664000, C438S682000
Reexamination Certificate
active
06750124
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed generally to fabrication of semiconductor devices and, more particularly, to a direct-write process for manufacturing ultra-thin metal silicide contacts, interconnects and structures in integrated circuits by focused ion beam implantation.
BACKGROUND
Semiconductor devices comprise integrated circuits that perform ever more complicated and faster operations. As device dimensions shrink, the devices must increase. These changes require refinement in integrated circuit design and manufacturing processes. Of especial importance is manufacture of contacts in technologies such as MEMS, MOSFETS, CMOS, nMOS, pMOS and BiCMOS.
In order to maintain speed in the devices, the contacts must have nanometer dimensions and have low resistivity. Transition metal silicides, especially titanium, cobalt and nickel have been used for this purpose.
However, shrinking device dimensions makes it increasingly difficult to fabricate high quality silicide contacts. For example, local stresses inherent at the encroaching boundaries of oxide or spacer layers pose problems for the growth of small self-aligned silicides (J. Y. Yew and L. J. Chen, J. Vac. Sco. Technol. B 17, 939—1999). Decreasing critical dimension also causes a downward shift in the agglomeration temperature of silicide phases (A. Stegen, I. D. Wolf, and K. Maex, Jr. Appl. Phys. 86, 4290—1999). This ultimately necessitates varied process conditions and affects variability.
Resist-based lithography, particularly photolithography, has generally been used in the fabrication process for VLSI circuits and is among the methods used for refining manufacturing processes and improving performance. In this technique, photoresistant masks are employed at selected fabrication process steps to prevent exposure to layering materials as a device is being built. The masks generally comprise polymers. However, the size of devices has reached the limits that can be achieved with masks. Morover, the processes are complicated, lengthy and environmentally unfriendly.
Direct write techniques have been proposed as alternative approaches for silicide fabrication. The use of masks usually limits features to about 1 to 2 micrometers in size, whereas direct writing permits features having dimensions of submicrometers. Bischoff et al. (L. Bischoff, K.-H. Heinig, J. Teichert, and W. Skorupa, Nucl. Instrum. Methods Phys. Res. B 112, 201 (1996)) have fabricated CoSi 2 structures by focused ion beam (FIB) implantation of Co (1) to form wires with dimensions as low as 250 nanometers. Fuhrmann et al. H. Fuhrmann, M. Do “beli, and R. Mu” hl., J. Vac. Sci. Technol. B 17945 (1999)) used FIB implantation to mask silicon by local desorption of hydrogen from an HF-passivated surface. This method was applied to produce 160 nm wide CoSi (II) wires in a Si/CoSi(II) heterostructure. Drouin, et al (D. Drouin, J. Beauvais, R. Lemire, E. Lavelle'e, R. Gauvin, and M. Caron, Appl. Phys. Lett. 70, 3020 (1997)) used electron-beam lithography, to produce nanometer-scale platinum suicides. This process, termed silicide direct write electron-beam lithography, relies on localized heating of thin platinum layers on silicon to initiate silicidation.
To meet the growing demand for smaller, faster semiconductor devices, new methods for producing reliable silicides having low resistivity and dimensions in the nanometer range continue to be sought.
SUMMARY
It is an object of the present invention to provide a direct-write process for forming localized transition metal suicides on a semiconductor substrate.
It is a further object of the present invention to provide MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS semiconductor devices comprising contacts, interconnects and structures formed by the present process.
The present invention provides a direct-write process for forming localized metal silicides at one or more selected areas on a silicon substrate using focused ion beam (FIB).
In the process, the substrate, preferably a silicon wafer, is treated to form a first barrier layer thereon and then a second metal layer on the barrier layer. A focused ion beam is directed through the barrier layer and the metal layer to the selected area of substrate. The FIB causes disruption of the barrier layer over the selected area of substrate. With a single low temperature anneal, metal and silicon react at this area to form metal silicides structures having nanometer dimensions on the substrate. The substrate is again annealed at a higher temperature, depending on the particular metal employed, to perfect the morphology of the silicides. Some metal systems such as nickel do not require a second anneal.
In an important aspect of the present invention, the process may be used to form low resistive, nanometer scale metal silicide structures between components of integrated circuits on a silicon substrate. In these instances the locations of the selected areas on the silicon substrate are chosen to be in contact with areas housing the components. The process for forming these structures comprises in addition the step of removing unreacted metal from areas not exposed to the focused ion beam after a first annealing step. Finally, the barrier layer outside areas exposed to the focused ion beam is removed.
In preferred instances of the invention, the metal is a transition metal or a rare earth element. Metal, for example, may be selected from the group comprising nickel (Ni), cobalt (Co), palladium (Pd), chromium (Cr), platinum (Pt), tungsten (W), vanadium (V), titanium (Ti), Indium (In), iridium (Ir), hafnium (Hf) and rubidium (Rb).
The barrier layer is preferably a silicon oxide or nitride.
In a preferred embodiment of the invention a direct-write process is given for formation of cobalt suicides on a silicon wafer. In the process, localized cobalt suicides are formed at one or more selected areas on a silicon substrate. In the process a substrate is provided, preferably a silicon wafer having a surface cleaned by any of the methods known in the art. A first barrier layer of silicon oxide is formed on the substrate, most preferably between 2 to 4 nanometers in thickness and a second cobalt layer, most preferably less than 50 nanometer in thickness, is formed on the barrier layer. A focused ion beam, preferably As
++
, is directed through the cobalt layer and the barrier layer to the selected substrate areas, under conditions whereby the barrier layer is disrupted at regions above the selected areas on the silicon wafer and cobalt is caused to react with silicon substrate at the disrupted barrier layer areas. The wafer is annealed at a first temperature of about 300° C. to 500° C. Unreacted cobalt is removed by a selective etch and the wafer is annealed at a second higher temperature of about 700° C. to 900° C. to enhance the morphology of the cobalt silicide. The wafer is finally etched to remove barrier formed outside the area exposed to the focused ion beam.
In an important aspect of the present invention, metal silicides formed at localized areas on a silicon by the process of the present invention are provided. The silicides have low resistivity and dimensions in the nanometer range. These properties make them especially suitable as contacts, interconnects and similar structures in integrated circuits in a large variety of semiconductor devices. Such devices may involve, for example, any of the technologies MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS.
REFERENCES:
Matsushita et al [“Narrow CoSi2 Line formatin on SiO2 by Focused Ion Beam”, Ion Implantation Technology 98, International Conference on Ion Implantation Technology Proceedings, 12th, Kyoto, Jun. 1998, vol. 2, pp 861-864].*
“Formation and Growth of CoSi2on (001)Si inside 0.2-2 &mgr;m oxide openings prepared by electron-beam lithography”; J.Y. Yew, et al.; May/Jun., 1999.
“Characterization of the local mechnaical stress induced during the Ti and Co/Ti salicidation in sub-0.25 &mgr;m technologies”; An Steegen, et al.; Oct. 15, 1999.
“Submicron CoSi2structures fabricated by focused
Alford Terry L.
Mayer James W.
Mitan Martin
Pivin, Jr. David P.
Arizona Board of Regents
Atkins Robert D.
Nguyen Thanh
Quarles & Brady Stretch Lang LLP
LandOfFree
Direct patterning of nanometer-scale silicide structures on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Direct patterning of nanometer-scale silicide structures on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Direct patterning of nanometer-scale silicide structures on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3328493