Direct memory access transfer control circuit

Details Direct memory access transfer control circuit Direct memory access transfer control circuit

2002-05-06

2004-05-11

Perveen, Rehana (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

C710S022000, C710S033000, C710S034000, C710S035000, C710S039000, C710S040000

Reexamination Certificate

active

06735639

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a direct memory access (DMA) transfer control circuit used for an information processing system.
2. Description of Related Art
FIG. 9
is a block diagram showing a conventional direct memory access transfer control circuit (DMAC). In
FIG. 9
,
1
indicates a conventional direct memory access (DMA) transfer control circuit.
10
1
,
10
2
, - - - and
10
N
(N is an integer equal to or higher than 2) indicate a plurality of channel control units respectively. The number N denotes the number of channels.
2
indicates a DMA transfer control unit. In the channel control units
10
1
to
10
N
, a plurality of transfer request holding circuits
20
1
,
20
2
, - - - and
20
N
are disposed respectively. In the DMA transfer control unit
2
, a channel transfer request arbitrating circuit
3
is disposed. A plurality of DMA transfer request signals DRQ
1
to DRQN corresponding to the channels respectively are sent from modules (not shown) other than the conventional DMA transfer control circuit
1
to the transfer request holding circuits
20
1
,
20
2
, - - - and
20
N
of the conventional DMA transfer control circuit
1
respectively.
Next, an operation of the conventional DMA transfer control circuit
1
will be described below.
When a DMA transfer request signal DRQn (n is an arbitrary integral number ranging from 1 to N) is input to the channel control unit
10
n
of the conventional DMA transfer control circuit
1
, the DMA transfer request signal DRQn is once held in the transfer request holding circuit
20
n
of the channel control unit
10
n
. Thereafter, the DMA transfer request signal DRQn held in the transfer request holding circuit
20
n
is fed to the DMA transfer control unit
2
as a channel transfer request.
Therefore, a plurality of DMA transfer request signals DRQ
1
to DRQN sent from the other modules are received in the DMA transfer control unit
2
as a plurality of channel transfer requests respectively. In cases where a plurality of channel transfer requests are received in the DMA transfer control unit
2
, the arbitration among the channel transfer requests is performed in the channel transfer request arbitrating circuit
3
of the DMA transfer control unit
2
, and one channel transfer request is selected to determine the performance of a DMA transfer for the selected channel transfer request. In detail, priorities are set in advance for the channel transfer requests (or the channel transfer request signals). When a plurality of channel transfer requests are received in the DMA transfer control unit
2
, a DMA transfer is assigned to one channel transfer request (hereinafter, called a top priority channel transfer request) having the top priority among those of the channel transfer requests. Thereafter, the DMA transfer is first performed for the top priority channel transfer request in a prescribed procedure. When the DMA transfer for the top priority channel transfer request is completed, a DMA transfer for the second priority channel transfer request is performed. Thereafter, the DMA transfers for the other channel transfer request signals are performed one after another in the order of lowering the priority of the channel transfer request.
Because the conventional DMA transfer control circuit has the above-described configuration, it is impossible to grasp how long the performance of the DMA transfer for each channel transfer request having the priority lower than that of the top priority channel transfer request is delayed. In other words, a transfer waiting time period of the DMA transfer performed in response to each remarked channel transfer request signal depends on the number of received channel transfer request signals having priorities higher than that of the remarked channel transfer request signal, and it is impossible to grasp the transfer waiting time period of the DMA transfer in the module corresponding to the remarked channel transfer request signal.
Therefore, in cases where the priority set in advance for the remarked channel transfer request signal is low, it takes a long time to perform the DMA transfer in response to the remarked channel transfer request signal. Therefore, a problem has arisen that it is difficult to set optimum priorities for a plurality of channel transfer request signals of the other modules. Also, in cases where the transfer waiting time period for the DMA transfer is prolonged, there is probability that a system error occurs. Because it is impossible to grasp the transfer waiting time period, another problem has arisen that it is impossible to prevent the occurrence of a system error in advance.
SUMMARY OF THE INVENTION
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional DMA transfer control circuit, a DMA transfer control circuit in which a transfer waiting time period for a DMA transfer is shortened to efficiently perform the DMA transfer.
The object is achieved by the provision of a direct memory access transfer control circuit, comprising transfer control means for receiving N (N denotes an integral number equal to or higher than 2) DMA transfer requests composed of the first to N-th DMA transfer requests, assigning a plurality of DMA transfers to the N DMA transfer requests respectively according to priorities set in advance for the N DMA transfer requests and controlling the DMA transfers, and measuring means for measuring a time period from the reception of each DMA transfer request performed by the transfer control means to the assignment of the DMA transfer to the DMA transfer request performed by the transfer control means and outputting the time periods as a plurality of transfer waiting time periods of the N DMA transfer requests.
In the above configuration, in cases where a plurality of DMA transfers corresponding to a plurality of channels are performed, a transfer waiting time period from the reception of the DMA transfer request to the assignment of the DMA transfer can be grasped for each channel. Also, because the transfer waiting time period from the reception of the DMA transfer request to the assignment of the DMA transfer is grasped for each channel, the priority set for each DMA transfer request can be appropriately changed by comparing the transfer waiting time period of the DMA transfer request and a time before a system error occurs. Accordingly, the system error can be prevented.
It is preferred that the transfer waiting time period of each DMA transfer request is measured by the measuring means each time the DMA transfer request is received, and the transfer waiting time period longest among the time periods of one DMA transfer request is held by the measuring means as a maximum transfer waiting time period for each DMA transfer request.
Therefore, an operator can recognize the maximum transfer waiting time period for each DMA transfer request.
It is preferred that the transfer control means comprises a plurality of transfer request holding circuits for receiving the N DMA transfer requests respectively, holding the N DMA transfer requests respectively, and the measuring means comprises a plurality of counters for measuring a plurality of time periods from the holding of the DMA transfer requests in the transfer request holding circuits to the assignment of the DMA transfers to the DMA transfer requests in a count operation as the transfer waiting time periods of the N DMA transfer requests.
Therefore, the transfer waiting time period can be reliably measured for each DMA transfer request.
It is preferred that the direct memory access transfer control circuit further comprises a storing circuit for storing the transfer waiting time periods of the N DMA transfer requests, and reading means for selecting one of the transfer waiting time periods and reading out the selected transfer waiting time period.
Therefore, because the transfer waiting time period is stored in the storing means for each DMA transfer request, the order of the DMA transfers

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