Direct memory access system and method

Details Direct memory access system and method Direct memory access system and method

2008-03-14

2010-11-16

Tsai, Henry W (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

Reexamination Certificate

active

07836221

ABSTRACT:
A DMA system includes at lease one read bus, at least one write bus, at least one buffer memory bus, and a DMA controller. The DMA controller comprises a plurality of channels and a bus arbiter. The channels are electrically connected to the read bus, the write bus, and the buffer memory bus. A source address and a destination address of data for each channel are assigned by a control table. The bus arbiter performs bus arbitration and prioritizes data access among the read bus, the write bus, and the buffer memory bus.

REFERENCES:
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patent: 6763029 (2004-07-01), Trevitt et al.
patent: 2005/0114742 (2005-05-01), Takenobu
patent: 2005/0216612 (2005-09-01), Usui

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