Direct memory access engine for supporting multiple virtual...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing

Reexamination Certificate

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Details

C710S040000, C710S120000, C709S230000

Reexamination Certificate

active

06260081

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to direct memory access control in microcontrollers, and more particularly to a direct memory access engine for supporting multiple virtual direct memory access channels.
2. Description of the Related Art
MICROCONTROLLERS
As technology advances, computer system components are providing specific services which previously were offered by a microprocessor or the computer system as a whole. A centerpiece of this advancing technology is known as a microcontroller, or embedded controller, which in effect is a microprocessor as used in a personal computer, but with a great deal of additional functionality combined onto the same monolithic semiconductor substrate (i.e., chip). In a typical personal computer, the microprocessor performs the basic computing functions, but other integrated circuits perform functions such as communicating over a network, controlling the computer memory, and providing input/output with the user.
In a typical microcontroller, many of these functions are embedded within the integrated circuit chip itself. A typical microcontroller, such as the Am186EM or AM186ES by Advanced Micro Devices, Inc., of Sunnyvale, Calif., not only includes a core microprocessor, but further includes a memory controller, a direct memory access (DMA) controller, an interrupt controller, and both asynchronous and synchronous serial interfaces. In computer systems, these devices are typically implemented as separate integrated circuits, requiring a larger area and increasing the size of the product. By embedding these functions within a single chip, size is dramatically reduced, often important in consumer products.
From a consumer products designer's viewpoint, often the particular combination of added features make a particular microcontroller attractive for a given application. Many microcontrollers are available that use the standard 80×86 microprocessor instructions, allowing for software to be easily developed for such microcontrollers. Because of the similar execution unit instruction sets, the added features often become principal differentiating criteria between particular microcontrollers.
In implementing microcontrollers in embedded systems, another common requirement or desirable feature is the reduction of the bandwidth needed by any particular portion of the microcontroller in negotiating with other portions. For example, the core of a microcontroller is the execution unit, which is essentially a microprocessor core. An execution unit should be free to perform the programmed task to which it is dedicated, rather than spending time waiting on other units within the microcontroller.
DIRECT MEMORY ACCESS
Often helpful in freeing up the execution unit are direct memory access (DMA) units, timer control units, and interrupt control units. Such units off-load the tasks of waiting for certain external transactions to take place, and, in the case of the DMA unit, actually off-loading the task itself. The DMA unit can be programmed to perform transfers between memory locations, between input/output ports, or between a memory location and an input/output port. Off-loading these tasks, the execution unit is freed from having to wait for such transfers to take place, and as such, can increase the overall speed of the computer system.
The DMA unit functions, without involving the microprocessor, by initializing control registers in the DMA unit with transfer control information. The transfer control information generally includes the source address (the address of the beginning of the block of data to be transferred), the destination address (the address where the beginning of the block of data is to be transferred), and the size of the data block. While both a microprocessor and a DMA unit may store data internally before distributing data to a proper address, a DMA unit may provide address and bus control signals to and from a peripheral or memory device such that the peripheral or memory device can access a peripheral or memory device for a read or a write cycle.
Specific channels are implemented in a DMA unit to allow peripheral or memory devices to transfer data (with or without internal data storage by the DMA unit) to or from other peripheral or memory devices. A channel can be activated via a DMA request signal (DREQ) from a peripheral or memory device. The DMA unit receives the DREQ, provides a DMA acknowledge signal (DACK) or simulated version thereof, and transfers the data over the channel to or from the peripheral or memory device. Peripheral devices which commonly use DMA channels include DRAM (dynamic random access memory) refresh circuitry, sound cards, SCSI host adapters, parallel ports, tape cards, network cards, modems, and floppy disk controllers.
Direct memory access channels have traditionally been supported in hardware and managed by control logic within a direct memory access controller. This control logic has typically taken the form of multiple registers (e.g., DMA command registers, DMA mode registers, DMA status registers, DMA mask registers, DMA request registers, DMA count registers, and DMA address registers) which take up valuable silicon space. Each direct memory access channel has been associated with its own portion of the control logic (e.g., DMA count registers and DMA address registers).
SUMMARY OF THE INVENTION
Briefly, the present invention provides a direct memory access engine for supporting multiple virtual direct memory access channels. The direct memory access engine includes a direct memory access controller and a parameter table in memory containing parameters for a plurality of virtual direct memory access channels. The direct memory access engine provides a single physical direct memory access channel and a plurality of virtual direct memory access channels. One channel of the plurality of virtual direct memory access channels may be active at a given time. The parameters for the active channel are loaded from the parameter table to the direct memory access controller. A physical direct memory access control block of the direct memory access controller utilizes a physical direct memory access channel resource to perform a direct memory access transfer for the active channel based on the loaded parameters. The physical direct memory access channel resource of the controller is shared by the plurality of virtual direct memory access channels. The direct memory access engine further includes a direct memory access request line and a direct memory access acknowledge line for an active channel of the plurality of virtual direct memory access channels.
The present invention eliminates the need for each direct memory access channel to be associated with its own control logic. In this way, memory is used to store direct memory access control information for a single direct memory access channel rather than consuming large areas of silicon with direct memory access control logic for multiple direct memory access channels.


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DMA Controller, Advanced Micro Devices, Inc., Chapter 9, pp. 9-1 through 9-14.
The Indispensable PC Hardware Book, Second Edition, Hans-Peter Messmer, Chapter 25, pp. 598-621.
International Search Report, PCT/US99/14797, Oct. 13, 1999, 3 pp.

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