Direct memory access controller with split channel transfer...

Details Direct memory access controller with split channel transfer... Direct memory access controller with split channel transfer...

2000-08-08

2001-10-30

Lee, Thomas (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S028000, C710S035000, C710S052000

Reexamination Certificate

active

06311234

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to microprocessors, and particularly relates to microprocessors which include a direct memory access feature.
BACKGROUND OF THE INVENTION
Microprocessor designers have increasingly endeavored to improve performance in various microprocessors by increasing clock speeds and adding parallelism. Large blocks of random access memory (RAM) are included within the microprocessor for data storage and for program storage in order to reduce memory access times. Direct Memory Access (DMA) circuitry is often provided to transfer data between peripheral devices connected to a microprocessor and memory connected to the microprocessor. DMA circuitry is initialized and a DMA transfer operation monitored by software which operates on the microprocessor. DMA circuitry may provide one or more channels of independent control. A detailed description of a six channel DMA controller is contained in U.S. Pat. No. 5,305,446, issued to Leach et al, which is incorporated herein by reference, particularly with reference to
FIGS. 10
,
11
,
12
a
and
12
b.
An object of the present invention is to reduce the amount of initialization and monitoring required of software operating on the microprocessor for a given DMA transfer operation.
Another object of the present invention is to allow variable transfer rates for receive and write transfers.
SUMMARY OF THE INVENTION
In general, and in a form of the present invention, a microprocessor which has a central processing unit (CPU) and an internal memory, is further equipped with direct memory access (DMA) circuitry which is operable to transfer data from an external source of data to the internal memory. DMA interrupt circuitry interrupts the CPU in order to indicate transfer completion. A peripheral device within the microprocessor is provided with address generation circuitry for transferring data to or from the internal memory. An auxiliary channel control circuit is provided which causes data to be transferred to the internal memory using the address generation circuitry of the peripheral device and to interrupt the central processor using the DMA interrupt circuitry of the DMA controller.
In another aspect of the present invention, the DMA controller has programmable read address circuitry and programmable write address circuitry.
Another embodiment of the present invention has circuitry for performing split channel operation, operable to transmit data from a source address to a split destination address, and operable to coincidentally receive data from a split source address to a destination address.
Another embodiment of the present invention includes global data registers which can be used by the DMA controller for different functions on subsequent transfer operations.
Another embodiment of the present invention includes a floating FIFO buffer which can be connected between a selected source bus and a selected destination bus.
Other embodiments of the present invention will be evident from the description and drawings.


REFERENCES:
patent: 5335326 (1994-08-01), Nguyen et al.
patent: 5381538 (1995-01-01), Amini et al.
patent: 5655151 (1997-08-01), Bowes et al.
patent: 5732223 (1998-03-01), Moore et al.
patent: 5765023 (1998-06-01), Leger et al.
patent: 5828856 (1998-10-01), Bowes et al.
patent: 5831393 (1998-11-01), Hohenstein et al.
patent: 5974486 (1999-10-01), Siddappa
patent: 6081854 (2000-06-01), Priem et al.
patent: 6167465 (2000-12-01), Parvin et al.
patent: 6226338 (2001-05-01), Earnest

Affiliated with

Also associated with

Rating

Direct memory access controller with split channel transfer... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Direct memory access controller with split channel transfer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Direct memory access controller with split channel transfer... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2595462