Direct memory access controller having decode circuit for...

Details Direct memory access controller having decode circuit for... Direct memory access controller having decode circuit for...

1999-02-10

2002-09-17

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S052000, C711S111000

Reexamination Certificate

active

06453365

ABSTRACT:

TECHNICAL FIELD
The present invention generally relates to computer systems, and more particularly to a direct memory access (DMA) controller.
BACKGROUND OF THE INVENTION
As is well known, DMA transfers involve the movement or transfer of data from one memory device to another memory device (within a computing system) across a system bus, and without intervening communication through a processor. More particularly, a processor such as a CPU typically controls and coordinates the execution of instructions within computing system. Ancillary to this operation, the CPU must frequently move data from a memory or other peripheral device into the CPU for processing, or out of the CPU to a memory or other peripheral device after processing. The CPU also often coordinates the movement of data from one memory or peripheral device to another memory or peripheral device.
In very early computing systems, this latter movement of data was accomplished by first reading the data directly from one memory device into the processor, then immediately writing that same data out to another memory device. As computing systems advanced, DMA controllers were created to facilitate such data transfers by controlling the movement of data directly from one memory device to another memory device.
FIG. 1
shows a block diagram illustrating certain fundamental components of a computer system that are utilized in connection with such a conventional DMA transfer. In this regard, a single DMA controller
10
is illustrated in connection with a source memory
12
, a destination memory
14
and a CPU or some other processing circuit
16
. Each of the devices is illustrated as being interconnected, or otherwise disposed for intercommunication, via a bus
18
, which preferably comprises both address and data lines. The devices are also interconnected through various control and other signaling lines
19
,
20
,
21
, and
22
. In operation, data
24
may be directly transferred between memory devices
12
and
14
across the bus
18
, without having to transition through the CPU
16
, which allows data to be transferred between the memories at a much higher rate.
As is known, there are three primary steps involved in a DMA transfer. First, the processor
16
sets up the DMA transfer by supplying a DMA controller
10
with the identity of the source and destination memories
12
and
14
, the address of the first byte to be transferred from the source memory
12
, as well as the number of bytes to be transferred. Once the CPU
16
has communicated this information to the DMA controller
10
, the DMA controller
10
starts the operation by either taking control of the bus
18
, or otherwise requesting shared control of the bus with other devices (not shown). In this regard, other devices that are disposed along the same bus
18
may share the bus, the allocation of which may be controlled by an arbitration circuit (not shown), as is understood by those skilled in the art. Once the DMA controller
10
has the bus
18
, it initiates the bus transfer (assuming that the data is available for transfer). In this regard, and as will be understood by persons skilled in the art, if the data were temporarily stored within a cache memory, or some other device (not shown), then the data actually stored in the memory device
12
, would be considered “dirty data”, and therefore not subject to transfer. Resolution of nuances such as this are known by those skilled in the art, and need not be discussed herein, in order to effectively illustrate the basic DMA operations as are known by prior art systems.
Utilizing control lines
21
and
22
, the DMA controller
10
may orchestrate the transfer of data from the source memory
12
to the destination memory
14
. The DMA controller
10
may control the address supplied on address bus
18
, as well as the chip select and enable lines necessary in order to read data from a select memory address of the source memory
12
and write that same data to a select memory address in the destination memory
14
. Assuming that a plurality of data bytes are to be transferred from the source memory
12
to the destination memory
14
, then the DMA controller
10
will update the addresses on bus
18
accordingly. Once the DMA transfer is complete, the DMA controller
10
may interrupt the CPU
16
to inform it accordingly. It will be appreciated that throughout the duration of the DMA transfer, the CPU
16
may be performing various processing operations. As is known, this greatly enhances the overall efficiency of the system by allowing the CPU
16
to perform processing tasks, without having to get bogged down in managing simple data transfers between memory devices.
Notwithstanding the various advantages and efficiency gains achieved by DMA devices, there is a constant desire to improve on performance. One manner in which performance improvements have been obtained is through the use of DMA controllers that include the ability to execute commands. In such devices, as the DMA controller operates, it may program itself with a self-executing command and start a DMA cycle according to the command.
One way of structuring the execution of such commands is to organize an area of external memory (e.g., ROM or RAM) to store the commands, as well as all the data required for executing the command. Since this information must be communicated from the external memory into the DMA controller, it is important to limit the quantity of information that must be communicated from the memory to the DMA controller, thereby maximizing the bus bandwidth.
There is, therefore, a need for a system that provides an efficient command structure for execution by a DMA controller.
SUMMARY OF THE INVENTION
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the foregoing and other objects, the present invention is directed to an improved direct memory access (DMA) controller for executing commands having an extremely compact structure, and which may be stored in an external memory. In accordance with one aspect of the present invention, a DMA controller is provided having circuitry configured to receive a memory segment, wherein the memory segment comprises a plurality of contiguous bytes from an external memory. The DMA controller also includes circuitry configured to parse the received memory segment into a plurality of distinct segments. The controller also includes circuitry configured to store the plurality of distinct segments into a plurality of internal registers, wherein the plurality of internal registers includes a command register. Finally, the DMA controller includes circuitry configured to decide the value stored in the command register to identify an instruction for execution.
In accordance with one embodiment of the invention, decode circuitry is configured to receive an eight byte memory segment, parse the eight byte memory segment and store the eight bytes in a plurality of registers disposed within the DMA controller. In accordance with this embodiment, the decode circuitry further includes a first segment for parsing a first two-byte segment and storing the first two-byte segment in an internal start address register, a second segment for parsing a second two-byte segment and storing the second two-byte segment in an internal data length register, a third segment for parsing a first one-byte segment and storing the first one-byte segment in an internal command register, a fourth segment for parsing a second one-byte segment and storing the second one-byte segment in an internal extra byte register, and a fifth segment for parsing a third two-byte segment and storing the third two-byte segment in an internal “ext

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