Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2001-12-18
2004-01-27
Shin, Christopher B. (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S035000, C710S308000, C710S310000
Reexamination Certificate
active
06684267
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a used for transferring data between a buffer area formed on a memory and another area on the memory or an input/output unit without using a CPU of a computer system.
BACKGROUND OF THE INVENTION
In general, the data transfer operation by direct memory access is faster than the operation when a CPU transfers data in accordance with control by a program. Therefore, the direct memory access operation is frequently used for data transfer between a high-speed input/output unit and a memory, that is, data transfer relating to the input/output operation.
In the case of a computer system, a ring buffer is set on a memory in accordance with the control by a program executed by a CPU and data may be transferred between the ring buffer and an input/output unit. In the case of the system of this type, the data read from an input apparatus is temporarily stored in a ring buffer to wait for the processing by a CPU to start. Moreover, the data processed by the CPU is temporarily stored in the ring buffer while waiting for the data to be output from an output unit and then successively fetched from the ring buffer and sent to the output unit.
Among recent direct memory access controllers, there is a controller making it possible to perform the direct memory access transfer using a ring buffer as a data transfer destination or data transfer source by adding a function for generating an address so as to circulate through a constant area serving as a ring buffer on a memory and access the area and a function for detecting that the ring buffer is full and stopping the transfer operation. It is possible to continue transfer of data because a data write position is returned to the head of the ring buffer by the above address-generating function even if the data write position reaches the end of the ring buffer while incrementing an address and transferring the data to the ring buffer.
The above address-generating function is realized by suppressing the carry from a low-order specific bit to a high-order bit when calculating an address. For example, when using a 64 KB ring buffer for a 32-bit-byte-addressing system, the carry from low-order 16 bits to the 17th bit is suppressed. Thus, because digits higher than the 17th bit are not updated, it is possible to circulate through and access a 64 KB memory area designated by high-order 16 bits. Moreover, to realize the above address-generating function, it is also allowed to set an initial value to an address register again when completing transfer of the data same amount as the size of a memory area assigned to a ring buffer.
Moreover, in the case of a system expanded so as to access a ring buffer by adding only a function for generating the above circulating address to a conventional direct memory access controller which does not access a ring buffer, the above transfer-operation-stopping function is realized by designating a stopping condition by a transferred amount of data. In this case, the size of an empty area in a ring buffer is designated as a transferred amount of data and the data transfer operation stops when the ring buffer becomes full, that is, the size of the empty area in the ring buffer becomes zero.
Furthermore, to realize the above-mentioned transfer-operation-stopping function, it is allowed to provide a flag for the data in the ring buffer and detect an empty area in the ring buffer by the flag. For example, when the minimum unit for transfer with the ring buffer is a word, a flag showing whether the word is empty or not is provided for each word. Then, a value showing not being empty is set to a flag corresponding to a memory area in which data is written. Moreover, a value showing being empty is set to a flag corresponding to a memory area from which data is read. When a value showing not being empty is set to all flags, the data transfer operation stops.
However, to realize the above address-generating function by suppressing the carry from a low-order specific bit to a high-order bit, there is a disadvantage that the size of a memory area used for a ring buffer is restricted to 2n bytes (where n is an integer). Moreover, there is a disadvantage that the head address of a buffer area must be present at a 2n-byte boundary. However, to realize the above address-generating function by setting an initial value to an address register again, a register having bits equal to the number of address bits is necessary in order to hold the value to be set again and thereby, a circuit size increases.
Moreover, to realize the above transfer-operation-stopping function by designating the size of an empty area in a ring buffer as the transferred amount of data, there is a problem that the transfer capacity of a direct memory access controller is suppressed because it is difficult to perform the parallel processing with software to be executed by a CPU. For example, a case is considered in which a direct memory access controller stores the data read from an input apparatus in a ring buffer by means of direct memory access transfer and the software to be executed by a CPU fetches processes the data. In this case, the direct memory access controller decreases the transferred amount of data in accordance with the transferred amount of data whenever transferring data to the ring buffer. However, the CPU fetches data from the ring buffer, frees an area in the ring buffer in accordance with the fetched amount of data, and increases the transferred amount of data in accordance with the size of the freed area.
Because a CPU using a load/store architecture does not have a function for exclusively updating a value stored in a memory, the CPU requires operations of three stages of loading the transferred amount of data in a register, increasing the loaded value, and then rewriting the value when updating the transferred amount of data. When a direct memory access controller updates the transferred amount of data in the middle of these three stages, the transferred amount of data is not correctly updated. Therefore, to prevent that the CPU and the direct memory access controller update the transferred amount of data at the same time, the direct memory access controller temporarily stops operations while the CPU updates the transferred amount of data. For this reason, the transfer capacity of the direct memory access controller is suppressed.
Moreover, to realize the above transfer-operation-stopping function by providing a flag for the data in the ring buffer, there are problems that an extra memory is consumed by the flag and that a memory area assigned to the flag must be initialized when starting using a certain area of the memory as a ring buffer.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a direct memory access controller capable of direct-memory-access-transferring data by using a ring buffer as an access object without increasing a circuit size or lowering a transfer capacity for direct memory access, having high versatilities of the size and address of a memory area assigned to the ring buffer, and moreover capable of reducing a memory capacity required to access the ring buffer. Moreover, it is another object of the present invention to provide a direct memory access method capable of direct-memory-access-transferring data by using a ring buffer as an access object without deteriorating the transfer capacity of direct memory access.
To achieve the above objects, the present invention is provided with a first register (SBA register) which stores the base address of a transfer-source area, a second register (DBA register) which stores the base address of a transfer-destination area, a third register (PIX register) which stores a data read position in the transfer-source area as the offset from the base address stored in the first register, a fourth register (SIX register) which stores a data write position in the transfer-destination area as the offset from the base address stored in the second register, and a fifth register (BCL register) which stores a value that ind
Fujitsu Limited
Shin Christopher B.
Staas & Halsey , LLP
LandOfFree
Direct memory access controller, and direct memory access... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Direct memory access controller, and direct memory access..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Direct memory access controller, and direct memory access... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3255777