Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-12-02
2002-10-08
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S062000, C710S072000, C710S068000, C710S308000
Reexamination Certificate
active
06463481
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a digital scanner for scanning images. More specifically, the present invention is directed to a method and apparatus for accurately scanning documents and for processing digital data to provide digital images stored in memory, which can be retrieved for printing on support material or for displaying on a display screen.
BACKGROUND OF THE INVENTION
In a conventional digital scanner, a light source is used to illuminate a document having the image to be scanned. The conventional digital scanner also includes a platen glass upon which the document rests and a platen cover. The light emmitted by the light source illuminates the document and is reflected off and imaged by an optical system or lens system towards either a CCD sensor array or full width array, which converts the reflected light into electrical signals which are eventually converted into digital image data. An image processing circuit electronically registers the image, and converts the electrical signals into digital image data so that the digital image data can be utilized by an image output terminal, network citizen, or memory device.
In the prior art, a printer or other digital imaging system is typically coupled to a digital scanner for scanning an original image (e.g. document) and. employs an initial step of charging a photoconductive member (photoreceptor) to a substantially uniform potential. The charged surface of the photoconductive member is thereafter exposed to a light image of an original document to selectively dissipate the charge thereon in selected areas irradiated by the light image. This procedure records an electrostatic latent image on the photoconductive member corresponding to the informational areas contained within the original document being reproduced. The latent image is then developed by bringing a developer including toner particles adhering triboelectrically to carrier granules into contact with the latent image. The toner particles are attracted away from the carrier granules to the latent image, forming a toner image on the photoconductive member, which is subsequently transferred to a copy sheet. The copy sheet having the toner image thereon is then advanced to a fusing station for permanently affixing the toner image to the copy sheet.
The approach utilized for multicolor electrostatographic printing is substantially identical to the process described above. However, rather than forming a single latent image on the photoconductive surface in order to reproduce an original document, as in the case of black and white printing, multiple latent images corresponding to color separations are sequentially recorded on the photoconductive surface. Each single color electrostatic latent image is developed with toner of a color complimentary thereto and the process is repeated for differently colored images with the respective toner of complimentary color. Thereafter, each single color toner image can be transferred to the copy sheet in superimposed registration with the prior toner image, creating a multi-layered toner image on the copy sheet, Finally, this multi-layered toner image is permanently affixed to the copy sheet in substantially conventional manner to form a finished copy.
SUMMARY OF THE INVENTION
In one embodiment, there is a direct memory access controller, coupled to a data compression unit and FIFO, for storing digital data in a memory comprising: a compression and decompression bus control logic unit; a bypass interface; a data selector; a computing unit instructing the data selector to select the routing of digital data by way of the bypass interface or by way of the compression and decompression bus control logic unit; a data packer receiving the selected digital data from the data selector and packing the digital data into words; and a write DMA master receives the words of digital data from the data packer and places the words into blocks of digital data and stores the blocks of digital data in the memory. The blocks of digital data are transferred from the direct memory access controller to the memory by way of a video bus.
The data compression unit can be one of a JPEG and ITU G3/G4. The direct memory access controller further comprises a second data compression unit, wherein the data compression unit is an ITU G3/G4 and the second data compression unit is a JPEG. The data selector transmits the selected data in packets to the data packer. The data packets can comprise one of eight bits, sixteen bits and 24 bits. The data packer rearranges the digital data to form words of digital data having a required bit length. The bit length of the words can be thirty-two.
The write DMA master includes registers. The registers configure starting addresses and block size for a front block of digital data and a back block of digital data in the write DMA master, wherein the front block of digital data is the block of digital data currently being transferred by the write DMA master and the back block of digital data is the next block of digital data to be transferred by the write DMA master. The back block of digital data is subsequently copied into the front block for transfer and the write DMA master subsequently interrupts a computing unit, which transmits the new address and block size of the next back block. The write DMA master includes an internal FIFO. The write DMA master monitors the write DMA master internal FIFO threshold so that when enough digital data has been written to the internal FIFO, the digital data is burst onto a video bus for storage in the memory. The write DMA master includes an address counter, a data counter and a main state machine for video bus phase control.
A direct memory access method for storing digital data, comprising: (a) initializing DMA controller having a write DMA master; (b) scanning images to provide digital data to a data packer; (A c) writing words of digital data from data packer to write DMA master internal FIFO; (d) writing digital data to memory starting at the front block address in bursts until the transfer of digital data for the front block is completed; (e) loading write DMA master back block address and size into front block and next block address and size into write DMA master front block; and (f) repeating steps (c) through (e) while performing step (c) until all of the images are scanned and all of the digital data is stored in memory.
The digital data is compressed by a data compression unit before the data packer receives the digital data. The data compression unit is one of a JPEG and ITU G3/G4. The data compression unit further comprises selecting a data compression unit from a plurality of data compression units to compress the digital data and compressing the digital data before the data packer receives the digital data. The data compression units can be a JPEG and ITU G3/G4.
A direct memory access method for storing digital data, comprising: (a) initializing image processing unit and data compression unit; (b) selecting path is of digital data in DMA controller; (c) setting width of words of digital data in data packer; (d) initializing write DMA master front block and back block addresses and sizes; (e) setting threshold and burst size of write DMA master internal FIFO; (f) enabling write DMA master; (g) scanning images to provide digital data; (h) writing words of digital data from data packer to write DMA master internal FIFO for front block; (i) writing digital data to memory starting at the front block address in bursts until the transfer of digital data for the front block is completed; (j) loading write DMA master back block address and size into front block and next block address and size into write DMA master front block; and (k) repeating steps (h) through (j) while performing step (g) until the transfer of digital data is complete.
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patent: 4821107 (1989-04-01), Naito et al.
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patent: 5016114 (1991-05-01), Sakata et al.
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patent: 5031032 (1991-07
Chapin Robert M.
Frumusa Anthony M.
Lupien, Jr. Gordon F.
Daebeler P. F.
Gaffin Jeffrey
Xerox Corporation
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