Direct memory access channel controller with quick channels,...

Details Direct memory access channel controller with quick channels,... Direct memory access channel controller with quick channels,...

2006-05-12

2009-06-09

Tsai, Henry W. H. (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S025000, C710S026000, C710S028000, C710S308000, C709S212000, C711S001000

Reexamination Certificate

active

07546391

ABSTRACT:
A data transfer control apparatus includes a channel controller and a transfer controller. The channel controller receives, prioritizes and queues event signals and predetermined memory writes which trigger data transfer requests controlling the transfer controller. The event queue stores event numbers mapped to parameter memory locations storing data transfer parameters. The mapping table and the parameter memory are writeable via a memory mapped write operation. Memory protection registers store data indicative of permitted data accesses to the memory map.

REFERENCES:
patent: 5802583 (1998-09-01), Yeager et al.
patent: 6574683 (2003-06-01), Comisky et al.
patent: 6721822 (2004-04-01), Barry et al.
patent: 6856529 (2005-02-01), Radke
patent: 2003/0110325 (2003-06-01), Roach et al.
patent: 2005/0050241 (2005-03-01), Furuta et al.
patent: 2006/0080478 (2006-04-01), Seigneret et al.

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