Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Incorporating resilient component
Patent
1997-08-04
2000-08-22
Fahmy, Wael
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Incorporating resilient component
438119, 438613, 439 81, 439630, 439876, H01R 909
Patent
active
061071226
ABSTRACT:
A semiconductor package and method for fabricating the package are provided. The package includes a housing having individual channels, each adapted to retain a semiconductor die in electrical communication with electrical connectors. The dice can include solder bumps, formed on electrodes, using electroless deposition and wave soldering. For fabricating the package, the dice can be inserted into the channels, with the electrical connectors on the housing proximate to the solder bumps on the dice. The solder bumps can then be reflowed to form bonded connections with the electrical connectors. In an alternate embodiment, conductive adhesive bumps, rather than solder bumps, are formed on the dice to provide compliant connections with the electrical connectors on the housing. In addition, the conductive adhesive bumps can be cured while in contact with the electrical connectors to form bonded connections. Other alternate embodiments include a chip scale package, a temporary package for testing bare dice, and a multi chip module.
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Akram Salman
Farnworth Warren M.
Grigg Ford
Wood Alan G.
Eaton Kurt
Fahmy Wael
Gratton Stephen A.
Micro)n Technology, Inc.
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