Direct coupling field effect transistor logic (DCFL) circuit

Details Direct coupling field effect transistor logic (DCFL) circuit Direct coupling field effect transistor logic (DCFL) circuit

1998-11-18

2001-05-29

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

C326S112000, C326S117000

Reexamination Certificate

active

06239623

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a DCFL circuit, and in particular, to a DCFL circuit which includes an enhancement mode FET (EFET) and a depression mode FET (DFET) to operate at a high speed.
DESCRIPTION OF THE PRIOR ART
Heretofore, a DCFL circuit generally includes one DFET (D
1
) and one EFET (E
1
). An example of such a conventional DCFL circuit will be described by referring to
FIGS. 1
to
4
.
FIG. 1
shows a configuration example of a first example of the DCFL circuit, each includes one DFET (D
1
) and one EFET (E
1
). The EFET (E
1
) is arranged as a driving element and includes a gate electrode connected to an input terminal IN, a source electrode linked with a ground potential, and a drain electrode coupled with an output terminal OUT via a point at which a source electrode and a gate electrode of the DFET (D
1
) is connected (short-circuited) to each other. On the other hand, the DFET (D
1
) is adopted as a load element and includes the gate element and the source element connected to the output terminal OUT and a drain electrode coupled with a positive electrode.
FIG. 2
shows in a graph waveforms at respectively nodes of the circuit when the output potential changed from a low level (L) to a high level (H). When the input potential is at a low level (L), the EFET (E
1
) turns off and hence the output potential is set to a high level (H) determined by Vf of an EFET in its subsequent stage. When the input potential is at a high level (H), the EFET(E
1
) turns on. The output potential is set to a drain-source potential Vds which is developed when the gate is connected to the source in the DFET (D
1
), i.e., when a drain current ID equivalent to a drain current Idss flows through the EFET (E
1
).
To obtain a sufficiently low value of the low level (L), the ON current of the EFET (E
1
) is required to be satisfactorily larger than the drain current Idss of the DFET(D
1
). When the output potential changes from a high level (H) to a low level (L), the charge accumulated in the output load capacity is discharged by the ON current of the EFET (E
1
). In contrast thereto, when the output potential changes from the low level (L) to the high level (H), the output load capacity is charged by the drain current Idss of the DFET (D
1
). Therefore, when the load capacity is set to a large value, a propagation delay time tpd (↑) for the transition from the low output level (L) to the high output level (H) becomes very large when compared with a propagation delay time tpd (↓) for the transition from the high output level (H) to the low output level (L).
FIG. 3
shows a conventional example
2
including a configuration of an inverter circuit using a DCFL circuit to which a buffer circuit is added for a high-speed operation. This system includes a logic stage
21
, which is similar to the inverter circuit shown in
FIG. 1
, and a buffer circuit
22
including one DFET (D
2
) and two EFETs (E
2
and E
3
). The DFET (D
2
) includes a gate electrode connected to an output terminal N
21
of the logic stage
21
, a drain electrode linked with a positive power source, and a source electrode coupled with a drain electrode of the EFET (E
2
) and connected to an output terminal OUT. The EFET (E
2
) includes a gate electrode connected to an input terminal IN, a source electrode coupled with a ground potential, and the drain electrode linked with the source electrode of the DFET (D
3
) to be connected to the output terminal OUT as above. An EFET (E
3
) is disposed as a Schottky diode to clamp a high level (H) of a terminal N
21
.
FIG. 4
shows waveforms at respective nodes of the circuit when the output potential changes from a low level (L) to a high level (H). When the input potential changed from a high level to a low level, the potential of the output terminal N
21
alters from a low level to a high level as in the first conventional example. However, since the terminal N
21
is not associated with any heavy load, the delay time is short and the potential of the terminal N
21
increases at a high speed. On the other hand, although the potential of the output terminal OUT becomes equal to that of the terminal N
21
in terms of the direct current, the rising speed of the potential of the output terminal OUT is lower than that of the terminal N
21
when a large load capacity is connected to the output terminal OUT. That is, a high voltage Vgs is temporarily applied to the DFET (D
2
) and hence the current which charges the load becomes larger than the drain current Idss. Consequently, the rising speed of potential at the output terminal OUT becomes lower than that of the conventional example
1
as indicated by a dotted line. This increases the propagation delay time tpd (↑) and hence the operation speed is decreased.
The circuit configuration described above is attended with a problem that for a large load capacity, the propagation delay tpd (↑) in the transition from the low output level to the high output level becomes quite larger than the propagation delay time tpd (↓) in the reverse transition. The operation speed, which is slightly increased in the second example, is not satisfactory for practices. In addition, when the DFET is increased in size for a higher operation speed, the drain current Idss is increased, which leads to a problem of increase in the power consumption.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a DCFL circuit which operates at a high speed in a stable state regardless of the load capacity.
To achieve the object above in accordance with the present invention, there is provided a DCFL circuit including FETs. The circuit includes a buffer circuit and a pull-up circuit added to the buffer circuit for conducting a pull-up operation for a predetermined period of time when an output potential of the DCFL changes from a low level to a high level.
Additionally, the DCFL circuit includes a logic stage and a buffer circuit. The FETs include an enhancement mode FET and a depression mode FET.
In addition, the pull-up circuit includes an n-input NOR circuit. The NOR circuit including n input terminals, one enhancement mode FET, n FETs (n is an integer equal to or more than one), and n resistor elements. The enhancement mode FET includes a drain electrode connected to a positive power source, a gate electrode linked with an output terminal of the logic stage, and a source electrode coupled with drain electrodes of n FETs. The n FETs include drain electrodes connected to the source electrode of the EFET, gate electrodes each linked via a resistor element to an associated input, and source electrodes connected to the output terminal.
In this connection, the resistance value of each of the resistor elements is determined in accordance with a gate capacity of each FET of the pull-up circuit. The resistor element is an injection resistor, an epitaxial resistor, or a thin film resistor or an active element including a through FET.


REFERENCES:
patent: 4365172 (1982-12-01), Prater
patent: 4477735 (1984-10-01), Gollinger et al.
patent: 4798978 (1989-01-01), Lee et al.
patent: 5263001 (1993-11-01), Youn et al.

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