Direct backside interconnect for multiple chip assemblies

Wave transmission lines and networks – Long line elements and components – Strip type

Reexamination Certificate

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Details

C257S728000, C361S783000

Reexamination Certificate

active

06175287

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to the interconnection of signal lines and power lines among circuit chips such as monolithic microwave integrated circuits (MMICS) and electromechanical circuits supported on a common substrate and, more particularly, to an arrangement of vias passing through the circuit chip and normal to a surface of the substrate permitting the use of multiple bumps for batch processing of connections among components of plural chips such as MMICs in a multiple chip assembly (MCA).
In recent years, advances in the performance and ease of manufacture of gallium arsenide (GaAs) devices, MMICs, and MCAs have resulted in their utilization in numerous military and commercial systems. Essential to the utilization of this technology for construction of an MCA is the ability to form, repetitively and accurately, interconnects to MMIC chips and a common substrate which supports the chips. It has been the practice in the construction of an MCA to form RF (radio frequency) and dc (direct current) interconnects and control lines by wire or ribbon bonds.
A problem arises in that, at microwave and especially at millimeter-wave frequencies, bond wires in MCAs introduce a variable high series reactance and conductor loss. Such a wire bond may serve as a source of radiation and introduce increased electromagnetic coupling among components of the MCAs, with a resultant diminution in isolation among the components and possible occurrence of oscillations in circuits having high-gain blocks. This handicap becomes particularly noticeable with increasing frequency. Such degradation of performance is of particular importance at millimeter-wave frequencies.
SUMMARY OF THE INVENTION
The aforementioned problem is overcome and other advantages are provided by a form of interconnect which, in accordance with the invention, is implemented by a direct backside interconnect technology (DBIT) whereby a common substrate which supports the chips of an MCA is employed for interconnections among the chips by use of a set of vias passing through respective ones of the chips to communicate with the substrate. Chips of particular interest herein are integrated circuit chips (ICs) such as logic and amplifier circuit chips, chips having both electric circuit components and mechanical components, and MMICs. The vias pass through individual ones of the respective chips and are oriented normally to a surface of the substrate. The vias are arranged in accordance with matching arrangements of conductive strips on the substrate to permit use of multiple electrically conductive bumps, of substantially uniform size, for effecting electrical and physical interconnection by the vias to numerous circuit points within the various chips and corresponding terminals of stripline transmission lines within the common substrate. Additional vias may be employed for enhanced grounding of a chip by connection of a ground plate of the chip with a corresponding ground plate of the common substrate. Such additional vias may be employed also for isolation of signal lines and inhibition of oscillations. A ground plane on a bottom surface of a chip may be physically secured to a facing corresponding ground plane on a top surface of the substrate by a continuous layer of electrically conductive material, such as solder, or by a set of additional bumps.


REFERENCES:
patent: 5352998 (1994-10-01), Tanino
patent: 5406125 (1995-04-01), Johnson et al.
patent: 5635762 (1997-06-01), Gamand
patent: 5694300 (1997-12-01), Mattei et al.
patent: 5832598 (1998-11-01), Greenman et al.
patent: 5949140 (1999-09-01), Nishi et al.
patent: 310203 (1988-12-01), None

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