Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2000-08-07
2004-05-04
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S128000, C711S133000, C711S136000, C711S145000, C711S118000, C711S108000, C711S119000
Reexamination Certificate
active
06732234
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to digital systems and, more particularly, to caches within digital systems.
2. Description of the Related Art
Processors and/or the computer systems including the processors typically provide caches to alleviate the high memory latency frequently experienced in computer systems. Generally, a cache is a relatively small, high speed memory which may store copies of data corresponding to various recently-accessed memory locations. Generally, cache storage is allocated and deallocated in units of cache lines (a group of bytes from contiguous memory locations). In other words, the cache may include multiple entries, and each entry may include storage for a cache line of bytes. If requested data for an access is not in the cache (a “miss”), an entry is allocated for the cache line including the requested data and the cache line is filled into the allocated entry. Subsequently, the data may be found in the cache upon request (a “hit”). In some cases, a portion of the cache line (often called a “sector”) may be valid while other portions are invalid. However, the entire cache entry is allocated for the cache line if one or more of the sectors are valid.
It is generally necessary to test the memory (including cache memory) of an integrated circuit or system (e.g. after manufacture and prior to shipping to a customer) to ensure that the memory has no defects. Defects may occur due to contamination in the fabrication of the memory circuit, a problem with the masks used during the fabrication, or other manufacturing errors.
Typically, the testing of memories has been performed by including-hardware embedded in the memory or situated close to the memory to perform the testing. This hardware is typically referred to as built-in self test (BIST) hardware. Since the BIST hardware is used only for testing purposes, the BIST hardware must be as small (in terms of circuit area, e.g. numbers of transistors) as possible to minimize the cost of the BIST hardware. Thus, the testing strategies that may be applied by BIST hardware have generally been limited to those strategies that can be implemented using a minimal amount of hardware. Furthermore, if the BIST hardware itself is implemented incorrectly, false failures or incomplete test coverage may result. A more flexible method for testing a memory is therefore desired.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a cache as described herein. The cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions).
The direct access transactions may, for example, be used to perform testing of the cache memory. Direct access transactions may be used to read and/or write test data from specific cache entries. Advantageously, BIST hardware may be eliminated in favor of performing testing of the cache using direct access transactions. Accordingly, risks due to faulty implementation of the test strategy in hardware may be alleviated. If an error in the test implementation is made, the error may be corrected by changing the test transactions.
Furthermore, in one embodiment, a processor may be used to initiate the direct access transactions by executing a code sequence. Thus, flexibility may be achieved in the test algorithms used by coding appropriate code sequences. More complex test algorithms may be more readily implemented using such a testing strategy than may be used for BIST hardware, since the requirement to keep the BIST hardware small and simple may be eliminated.
Still further, since the test is based on transactions received by the cache, testing may be performed by any device capable of communicating with the cache. Accordingly, even if the processor is not functioning properly, the cache may be tested by another device.
As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). Thus, circuitry for ensuring that the cache resets to a known state may be eliminated. In embodiments employing error checking and correction (ECC) mechanisms, the ECC data may be initialized during the writing of data in response to the direct access transactions, eliminated spurious ECC errors that might occur if uninitialized data were read from the cache. Direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data.
In one embodiment, the cache may alter the state of its replacement policy in response to a direct access transaction explicitly specifying a particular way of the cache. The state may be altered such that a succeeding cache miss causes an eviction of the particular way. Such an embodiment may be used to enhance the test coverage achievable with direct access transactions by providing the flexibility of using memory transactions to store test data into the cache. Testing of tag information may be more thorough in such an embodiment. Furthermore, the combination of direct access transactions and the deterministic setting of the replacement policy may have other uses (e.g. for flushing a cache entry or all cache entries without requiring an explicit flush command).
Broadly speaking, a cache is contemplated. The cache includes a memory and a control circuit coupled to the memory. The memory includes a plurality of entries. Each of the plurality of entries is configured to store a cache line of data. The control circuit is configured to select a first entry of the plurality of entries for access responsive to a first transaction which explicitly specifies the first entry.
Additionally, a system is contemplated including a cache and a first circuit coupled to the cache. The cache includes a plurality of entries. Each of the plurality of entries is configured to store a cache line of data. The first circuit is configured to initiate a first transaction explicitly specifying a first entry of the plurality of entries. The cache is configured to select the first entry for access responsive to the first transaction.
A method for testing a cache is also contemplated. A first transaction is performed to cause first data to be stored in a first entry of a cache. A read transaction explicitly specifying the first entry subsequent to performing the first transaction. The second data returned in response to the read transaction is compared to the first data to detect if an error occurred in the first entry.
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Dickman Michael P.
Rowlands Joseph B.
Broadcom Corporation
Kim Matthew
Li Zhuo H.
Merkel Lawrence J.
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