Direct access controller

Details Direct access controller Direct access controller

2003-01-15

2004-07-06

Fleming, Fritz (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

C710S026000

Reexamination Certificate

active

06760790

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-74533, filed on Mar. 18, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a direct memory access controller (to be referred to hereafter as “DMAC”) in an LSI such as a microprocessor, and more particularly to a DMAC which is capable of reducing the number of registers and thereby reducing power consumption.
2. Description of the Related Art
In recent LSIs such as microprocessors, increases in speed and functionality tend to be accompanied by increases in power consumption. Meanwhile, demands are being made for battery-operated portable information devices such as portable telephones or digital still cameras that are highly functional and have a low power consumption.
DMAC is provided into microprocessors in order to reduce the load on the CPU. A DMAC functions in place of a CPU to perform direct access to internal memory and external memory, and is used to transfer large amounts of data, to repeat data transfer within the same memory region, and so on. When, for example, a portable telephone or the like is switched back to active mode from power down mode, data in a predetermined memory region are transferred to another memory region, and whenever the buffer data in the bus interface becomes full, these data are transferred repeatedly into a predetermined memory region. A DMAC is used at such times to read data from a transfer source memory region and write the data into a transfer destination memory region.
A transfer source address, a transfer destination address, a transfer count, and an address increase/decrease value are set by the CPU, thereby the DMAC reads data in a predetermined memory region and writes these data into another predetermined memory region independently of the operations of the CPU. This setting information is written into registers which are built into the DMAC for each source/destination combination (channel). Thus, the CPU can cause the DMAC to perform appropriate data transfer from a specific transfer source to a specific destination source simply by selecting a set channel.
The aforementioned setting information is written into a set of registers corresponding to each channel inside the DMAC. Accordingly, in the DMAC, one set of registers for setting the information necessary to perform the aforementioned DMA is provided for each channel. Further, since these registers operate sychronously with a clock, wiring is provided to supply a clock to each register. In order to supply these clocks, the clock supply wiring must be driven, and thus by increasing the number of clock supply wirings, power consumption increases.
Accordingly, it is a trend that more registers and wirings to supply clocks to these registers are provided inside a DMAC, and the scale of the circuit increases, and in accompaniment therewith, power consumption also increase.
In particular, when the same DMA transfer is repeated, a reload register is provided and the initially set information is stored in the reload register such that when the DMAC completes all of the data transfers, the information inside the reload register is reset. This type of reload register is typically provided in each channel, and as a result, increases in the number of registers and increases in power consumption tend to occur.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a DMAC which is capable of suppressing circuit scale and thereby also suppressing power consumption.
In order to achieve this object, a first aspect of the present invention is a direct memory access controller for transferring data from a transfer source memory region to a transfer destination memory region, comprising: a transfer source address calculation unit which has transfer source address registers corresponding to a plurality of channels and which generates a transfer source address whenever data transfer is performed; a transfer destination address calculation unit which has transfer destination address registers corresponding to the plurality of channels and which generates a transfer destination address whenever data transfer is performed; a transfer count calculation unit which has transfer count registers corresponding to the plurality of channels and which generates a remaining transfer count whenever data transfer is performed; and an address increase/decrease value setting unit which has address increase/decrease value registers corresponding to the plurality of channels, wherein the transfer source address calculation unit and/or said transfer destination address calculation unit calculate upon data transfer a transfer source address and/or transfer destination address for the following data transfer from the initially set transfer source address and/or transfer destination address, and wherein the transfer source address register and/or said transfer destination address register retain the initially set transfer source address and/or transfer destination address.
According to this first aspect of the invention, the transfer source address and/or transfer destination address are retained in the transfer source address register and/or transfer destination address register, and hence there is no need to provide a reload register. By eliminating a reload register provided in each channel, the circuit scale can be suppressed, whereby power consumption can also be suppressed.
A second aspect of the present invention in order to achieve the aforementioned object is a direct memory access controller for transferring data from a transfer source memory region to a transfer destination memory region, comprising: a transfer source address calculation unit which has transfer source address registers corresponding to a plurality of channels and which generates a transfer source address whenever data transfer is performed; a transfer destination address calculation unit which has transfer destination address registers corresponding to the plurality of channels and which generates a transfer destination address whenever data transfer is performed; a transfer count calculation unit which has transfer count registers corresponding to the plurality of channels and which generates a remaining transfer count whenever data transfer is performed; and an address increase/decrease value setting unit which has address increase/decrease value registers corresponding to the plurality of channels, wherein the transfer source address calculation unit and/or said transfer destination address calculation unit calculate upon data transfer the address at the time of the subsequent data transfer from the address at the time of the previous data transfer and store the address in the transfer source address register and/or transfer destination source register, and upon completion of a series of data transfers calculate the initially set address from the address at the time of completion and store the address in said transfer source address register and/or said transfer destination address register.
According to this second aspect of the invention, a new address is calculated whenever data transfer is performed, and when a series of data transfers is complete, the initially set address is calculated from the address at the time of completion and stored in a register. Hence there is no need to provide a register for reload, and as a result the circuit scale is suppressed, whereby power consumption can be reduced.


REFERENCES:
patent: 6684267 (2004-01-01), Hiji
patent: 2003/0177291 (2003-09-01), Hori et al.
patent: 2003/0200362 (2003-10-01), Hayashi et al.

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