Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-11
2002-07-09
Tsai, Jey (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S356000, C438S237000, C438S710000
Reexamination Certificate
active
06417544
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to a structure and manufacturing process of a semiconductor device which provides protection from plasma induced damage during integrated circuit device processing and more particularly to a semiconductor diode like device with a controllable trigger voltage to optimize the protection against plasma induced damage for different process requirements.
(2) Description of Prior Art
As is well known in the art, semiconductor devices are fabricated on a semiconductor substrate that is subjected to numerous processing operations. By way of example, a semiconductor device is typically subjected to several plasma etching operations, which are designed to pattern the various substrate, oxide and metallization layers and construct the desired circuit layout. Although plasma etching has become the etching process of choice, the intense energies used to create the etching plasma has had a degrading effect on thin sensitive gate oxides that lie under gate electrodes of a given circuit design. Specifically, the plasma that is generated in etching chambers is designed to bombard a layer being etched with a high concentration of electrons and positively charged ions. Unfortunately, these electrons and positively charged ions are known to induce intense currents through the gate oxides, which necessarily produce oxide degrading traps in the gate oxides.
As feature sizes for device decrease, the thickness of gate oxide layers decreases, thereby exacerbating the adverse impact of plasma charging damage. A conventional approach to the plasma charging damage protection comprises the formation of a diode as typified in
FIG. 1A
, connected to the polycrystatine silicon layer, i.e., gate electrode, thereby providing a discharge path for electrical charging during plasma processing.
The avalanche breakdown voltage of a diode with shallow trench isolation (STI) has been increased to the level where these devices are no longer very effective for plasma induced damage (PID) protection in deep-quarter-micron process. In this situation, the breakdown voltage of the diode tends to be higher than the gate oxide breakdown voltage. As seen in
FIG. 7A
, thin gate oxide breakdown is about −6.7 volts for a 0.25 um device. As shown in
FIG. 7B
, typical normal diode breakdown is about −12.7 volts, well above the breakdown level of the gate oxide. Therefore, it is very useful to have a new type of diode like device with a low and controllable trigger voltage for to different PID protection requirements.
Other structures have been used to protect against plasma damage. As shown in
FIG. 1B
, diodes stacked in parallel are sometimes used. This can have the effect of reducing the point where current flows, i.e. effectively reducing breakdown voltage, but has the problem of leakage current flow during normal device measurements and/or operation.
FIG. 1C
represents zener diode device X protection, which also has the potential problem of leakage current during normal measurements and/or operation. Again, it is very useful to have a new type of diode like device with a low and controllable trigger voltage and improved leakage characteristics for different PID protection requirements.
The following patents describe ESD protection devices.
U.S. Pat. No. 6,075,276 (Kitamura) discloses a protection circuit using zener diodes.
U.S. Pat. No. 6, 057,578 (Aiello et al.) shows a protection circuit with zener diodes.
U.S. Pat. No. 6,054,740 (Barret), U.S. Pat. No. 6,028,324 (Su et al.) and 6, 013, 927 (Bothra et al.) show related protection circuits.
SUMMARY OF THE INVENTION
Accordingly, it is the primary objective of the invention to provide a novel, effective structure and manufacturable method for protecting integrated circuits, in particular field effect transistor devices, from damage caused by plasma processes used during manufacturing.
It is a further objective of the invention to improve plasma induced damage (PID) protection by enabling the protection voltage threshold to be varied to meet process and device design requirements.
In addition, it is an objective of this invention to minimize or eliminate stress in gate oxides caused by current flow induced by plasma processes thereby maintaining gate oxide integrity.
It is yet another object of the invention to provide a manufacturable method for forming the PID protection structure while maintaining the required operating characteristics of the devices being protected.
The above objectives are achieved in accordance with the embodiments of the invention that describes a process and novel structure for a diode-like PID protection (DLPP) device. Beginning with a semiconductor substrate, typically P doped, a N-well, two N-well N+ contact regions, and substrate N+ and P+ contact regions are formed. In the invention, the DLPP has a metal layer disposed as a dummy antenna connected to a polysilicon (poly) gate. The DLPP is structured as a butting diode with a polysilicon layer gate element above the butting region. There is a N-well resistor (R) and capacitor (C) formed by the inherit electrical characteristics of the N-well, connected between the poly gate and P-substrate as a RC buffer element. The structure is completed with appropriate metal conductors for the electrical connection system. The DLPP has a function of a controllable gate with Zener-liked-trigger, in which the dummy antenna picks up a portion of the plasma charge to provide a gate voltage for the gate of the DLPP. There is a N type inversion layer or P type accumulation layer formed under the poly gate for positive or negative plasma charge. The junction of the zener diode is found in the interface between the N-type inversion layer and P+ substrate contact, or N+ substrate contact region and P-type accumulation layer. Changing the shape and the size of the dummy antenna changes the amount of charge acquired, and subsequently the trigger voltage of the DLPP. During normal IC operation, any accumulated charge with the poly gate and associated antenna is discharged through the N-well resistor (R), and therefore no channel inversion or accumulation layer is developed under the poly gate. Thus, no leakage problem is found with this structure during testing or normal operation.
Another embodiment of the invention uses a N doped substrate with a P well, two associated P+P-well contact regions and a N+ and P+ substrate contact region to provide improved PID protection. For this embodiment the second voltage source is typically Vdd.
REFERENCES:
patent: 5959311 (1999-09-01), Shih et al.
patent: 6013927 (2000-01-01), Bothra et al.
patent: 6028324 (2000-02-01), Su et al.
patent: 6054740 (2000-04-01), Barret
patent: 6057578 (2000-05-01), Aiello et al.
patent: 6075276 (2000-06-01), Kitamura
patent: 6353235 (2002-03-01), Watanabe
Jun Cai
Pei Yao
Zhong He Can
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L.S.
Saile George O.
Tsai Jey
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