Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2004-07-20
2009-11-03
Ghebretinasae, Temesghen (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C331S017000
Reexamination Certificate
active
07613267
ABSTRACT:
In a feedback system such as a PLL, the integrating function associated with a loop filter capacitor is instead implemented digitally and is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor to be integrated on the same integrated circuit die as the PLL. In some embodiments, an analog phase detector is utilized whose phase error output signal is delta-sigma modulated to encode the magnitude of the phase error using a digital (i.e., discrete-time and discrete-value) signal. This digital phase error signal is “integrated” by a digital integration block including, for example, a digital accumulator, whose output is then converted to an analog signal, optionally combined with a loop feed-forward signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent “size” of the integrating capacitor function provided by the digital integration block may be varied by increasing or decreasing the bit resolution of circuits within the digital block.
REFERENCES:
patent: 3968493 (1976-07-01), Last et al.
patent: 4237423 (1980-12-01), Rhodes
patent: 4371974 (1983-02-01), Dugan
patent: 4458214 (1984-07-01), Lakomy
patent: 5005016 (1991-04-01), Schmidt et al.
patent: 5027085 (1991-06-01), DeVito
patent: 5036294 (1991-07-01), McCaslin
patent: 5036298 (1991-07-01), Bulzachelli
patent: 5239561 (1993-08-01), Wong et al.
patent: 5373255 (1994-12-01), Bray et al.
patent: 5495512 (1996-02-01), Kovacs et al.
patent: 5559841 (1996-09-01), Pandula
patent: 5631933 (1997-05-01), Chu et al.
patent: 5734008 (1998-03-01), Shirasaki et al.
patent: 5774023 (1998-06-01), Irwin
patent: 5870003 (1999-02-01), Boerstler
patent: 5892407 (1999-04-01), Ishii
patent: 5896067 (1999-04-01), Williams
patent: 5942949 (1999-08-01), Wilson et al.
patent: 5977838 (1999-11-01), Nagoya et al.
patent: 5978426 (1999-11-01), Glover et al.
patent: 5986512 (1999-11-01), Eriksson
patent: 6008703 (1999-12-01), Perrott et al.
patent: 6011815 (2000-01-01), Eriksson et al.
patent: 6047029 (2000-04-01), Eriksson et al.
patent: 6075388 (2000-06-01), Dalmia
patent: 6075416 (2000-06-01), Dalmia
patent: 6125158 (2000-09-01), Carson et al.
patent: 6137372 (2000-10-01), Welland et al.
patent: 6147567 (2000-11-01), Welland et al.
patent: 6150891 (2000-11-01), Welland et al.
patent: 6151152 (2000-11-01), Neary
patent: 6167245 (2000-12-01), Welland et al.
patent: 6208211 (2001-03-01), Zipper et al.
patent: 6380703 (2002-04-01), White
patent: 6580376 (2003-06-01), Perrott
patent: 6590426 (2003-07-01), Perrott
patent: 6643346 (2003-11-01), Pedrotti et al.
patent: 6683506 (2004-01-01), Ye et al.
patent: 6686805 (2004-02-01), Cyrusian
patent: 6765445 (2004-07-01), Perrott et al.
patent: 0590323 (1994-04-01), None
patent: 62-81813 (1987-04-01), None
Andersson, L. I. et al, “Silicon Bipolar Chipset for SONET/SDH 10 Gb/s Fiber-Optic Communication Links,” IEEE Journal of Solid-State Circuits, vol. 30, No. 3, Mar. 1995, pp. 210-218.
Belot, D. et al., “A 3.3-V Power Adaptive 1244/622/155 Mbit/s Transceiver for ATM, SONET/SDH,” IEEE Journal of Solid-State Circuits, vol. 33, No. 7, Jul. 1998, pp. 1047-1058.
Gray, C. T. et al., “A Sampling Technique and Its CMOS Implementation with 1 Gb/s Bandwidth and 25 ps Resolution,” IEEE Journal of Solid-State Circuits, vol. 29, No. 3, Mar. 1994, pp. 340-349.
Masaru Kokubo et al, “FA 15.2: A Fast-Frequency-Switching PLL Synthesizer LSI with a Numerical Phase Comparator,” IEEE International Solid-State Circuits Conference, New York, vol. 38, Feb. 1, 1995, pp. 260-261, 376.
Shayan, Y. R. et al., “All Digital Phase-Locked Loop: Concepts, Design and Applications,” IEEE Proceedings-F/Radar and Signal Processing 136, Stevenage, Herts, GB, vol. 136, No. 1, Part F, Feb. 1, 1989, pp. 53-56.
Guiterrez G. et al, “2.488 Gb/s Silicon Bipolar Clock and Data Recovery IC for SONET (OC-48),” IEEE 1998 Custom Integrated Circuits Conference, pp. 575-578.
Guiterrez, G. and Kong, S., “Unaided 2.5 Gb/s Silicon Bipolar Clock and Data Recovery IC,” VIII-7, 1998 IEEE Radio Frequency Integrated Circuits Symposium, pp. 173-176.
Hogge, Charles R., Jr., “A Self Correcting Clock Recovery Circuit,” IEEE Journal of Lightwave Technology, vol. LT-3, Dec. 1985, pp. 1312-1314, re-printed as pp. 249-251.
Hu, T. H. and Gray, P. R., “A Monolithic 480 Mb/s Parallel AGC/Decision/Clock-Recovery Circuit in 1.2- μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1314-1320.
Jarman, David, “A Brief Introduction to Sigma Delta Conversion,” Application Note AN9504, Intersil Corporation, May 1995, pp. 1-7.
Kawai, K. et al., “A 557-mW, 2.5-Gbit/s SONET/SDH Regenerator-Section Terminating LSI Chip Using Low-Power Bipolar-LSI Design,” IEEE Journal of Solid-State Circuits, vol. 34, No. 1, Jan. 1999, pp. 12-17.
Lee, T. H. and Bulzacchelli, J. F., “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop,” IEEE Journal of Solid-State Circuits, vol. SC-27, Dec. 1992, pp. 1736-1746, re-printed as pp. 421-430.
Lee, T. H. et al., “A 2.5 V CMOS Delay-Locked Loop for an 18 Mbit, 500 Megabyte/s DRAM,” IEEE Journal of Solid-State Circuits, vol. 29, No. 12, Dec. 1994, pp. 1491-1496.
Perrott, M. et al., “A 27mW CMOS Fractional-N Synthesizer/Modulator IC,” 1997 IEEE International Solid-State Circuits Conference, Session 22, Communications Building Blocks II, Paper SP 22.2, 1997 Digest of Technical Papers, vol. 40, pp. 366-367, 487.
Perrott, M. et al., “A 27mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation,” IEEE Journal of Solid-States Circuits, vol. 32, No. 12, Dec. 1997, pp. 2048-2060.
Pottbacker, A. et al., “A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s,” IEEE Journal of Solid-State Circuits, vol. 27, No. 12, Dec. 1992, pp. 1747-1751.
Razavi, Behzad, “Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial,” Monolithic Phase-Locked Loops and Clock Recovery Circuits—Theory and Design, ed. B. Razavi, IEEE Press, N.Y., 1996, pp. 1-39.
Walker, R. C. et al., “A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission,” IEEE International Solid-State Circuits Conference, Session 19, Paper 19.1 Slide Supplement, 1998, pp. 19.1-1-19.1-11.
Walker, R. C. et al., “A 1.5 Gb/s Link Interface Chipset for Computer Data Transmission,” IEEE Journal on Selected Areas in Communications, vol. 9, No. 5, Jun. 1991, pp. 698-703.
Weston, H. T. et al., “A Submicrometer NMOS Multiplexer-Demultiplexer Chip Set for 622.08-Mb/s SONET Applications,” IEEE Journal of Solid-State Circuits, vol. 27, No. 7 Jul. 1992, pp. 1041-1049.
Willingham, S. et al., “An Integrated 2.5GHz ΣΔFrequency Synthesizer with 5 μs Settling and 2Mb/s Closed Loop Modulation,” 2000 IEEE International Solid-State Circuits Conference, Session 12, Paper TP 12.3, pp. 200-201, 457.
Baird Rex T.
Huang Yunteng
Perrott Michael H.
Ghebretinasae Temesghen
Silicon Laboratories Inc.
Zagorin O'Brien Graham LLP
LandOfFree
Digitally-synthesized loop filter method and circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Digitally-synthesized loop filter method and circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Digitally-synthesized loop filter method and circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4097717