Digitally controlled circuit for reducing the phase...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S376000, C375S371000, C375S149000, C375S372000, C332S103000, C332S127000

Reexamination Certificate

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06876710

ABSTRACT:
A digitally controlled circuit for reducing the phase modulation of a signal. The circuit has a multiphase clock generator that produces n phases of a clock that is m-times the signal. The circuit further has a multiplexer with n inputs for the n phases of the clock and with one output which supplies the output signal. The output signal and the signal are connected to the inputs of a phase comparator. The output signal of the comparator is supplied to a sigma-delta modulator whose output signals are used for controlling the multiplexer. A jittered input signal is compared in the phase comparator with a master clock. The determined phase difference is integrated in a sigma-delta modulator. The aim of the circuit is to generate a clock without jitter, digitally and without using external components. This circuit provides 20 dB/decade attenuation of the jitter received in the SYNC signal, based on the P-regulator characteristic.

REFERENCES:
patent: 5493243 (1996-02-01), Ghoshal
patent: 5502750 (1996-03-01), Co et al.
patent: 5534827 (1996-07-01), Yamaji
patent: 5602882 (1997-02-01), Co et al.
patent: 5834987 (1998-11-01), Dent
patent: 39 42 883 (1991-06-01), None
patent: 0 692 878 (1996-01-01), None
Published International Application No. WO 96/28889 (Wilson et al.), dated Sep. 19, 1996.

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