Motion video signal processing for recording or reproducing – Local trick play processing – With randomly accessible medium
Reexamination Certificate
2000-03-06
2003-04-15
Tran, Thai (Department: 2615)
Motion video signal processing for recording or reproducing
Local trick play processing
With randomly accessible medium
C386S349000, C386S349000, C386S349000, C386S349000
Reexamination Certificate
active
06549717
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
The present invention relates to a digital video signal record and playback device for recording and playing back a digital video signal, and more particularly to a digital video signal record and playback device for recording and playing back on a medium such as an optical disc or the like a digital video signal coded on the basis of a motion compensation prediction and an orthogonal conversion.
2. Description of Related Art
FIG. 1
is a block circuit diagram of a conventional optical disc record and playback device shown in the Japanese Patent Application Laid-Open No. HEI 4-114369 (1992). Referring to
FIG. 1
, reference numeral
201
denotes an A/D converter for converting a video signal, an audio signal or the like into digital information. Reference numeral
202
denotes a data compressing circuit,
203
a frame sector converting circuit for converting compressed data into sector data which is equal to integer times of a frame cycle,
204
an error correction coder for adding the error correction signal to sector data,
205
a modulator for modulating interference between codes in a recording medium into a predetermined modulation code to reduce the interference,
206
a laser driving circuit for modulating laser light in accordance with a modulation code, and
207
a laser output switch. Further, reference numeral
208
denotes an optical head for emitting laser light,
209
an actuator for tracking a light beam emitted from the optical head
208
,
210
a traverse motor for sending the optical head
208
,
211
a disc motor for rotating an optical disc
212
,
219
a motor driving circuit,
220
a first control circuit and
221
a second control circuit. Further, reference numeral
213
denotes a playback amplifier for amplifying a playback signal from the optical head
208
. Reference numeral
214
denotes a demodulator for obtaining data from a recorded modulation signal,
215
an error correction decoder,
216
a frame sector inverse converting circuit,
217
a data extending circuit for extending the compressed data,
218
a D/A converter for converting extended data into, for example, an analog video signal and an audio signal.
FIG. 2
is a block circuit diagram showing an inside structure of the data compressing circuit
202
in FIG.
1
. In
FIG. 2
, a digital video signal inputted from the A/D converter
201
is inputted into a memory circuit
301
. A video signal
321
outputted from the memory circuit
301
is provided as a first input of a subtracter
302
and a second input of a motion compensation predicting circuit
310
. An output of the subtracter
302
is inputted to a quantizer
304
via a DCT (discrete cosine transform) circuit
303
. An output of the quantizer
304
is provided as an input of a transmission buffer
306
via a variable-length encoder
305
. An output of the transmission buffer
306
is outputted to the frame sector converting circuit
203
. In the meantime, an output of the quantizer
304
is inputted to the inverse DCT circuit
308
via an inverse quantizer
307
. An output of the inverse DCT circuit
308
is provided as a first input of an adder
309
. An output
322
of the adder
309
is provided as a first input of a motion compensation predicting circuit
310
. An output
323
of the motion compensation predicting circuit
310
provided as to a second input of the adder
309
and a second input of the subtracter
302
.
FIG. 3
is a block circuit diagram showing an inside structure of the motion compensation predicting circuit
310
in FIG.
2
. In
FIG. 3
, the output
322
of the adder
309
is provided as an input terminal
401
a
while the output
321
of the memory circuit
301
is provided as an input terminal
401
b
. The signal
322
inputted from the input terminal
401
a
is inputted to a frame memory
404
a
or a frame memory
404
b
via a switch
403
. A reference picture outputted from the frame memory
404
a
is provided as a first input of a motion vector detecting circuit
405
a
. The video signal
321
inputted from the input terminal
401
b
is inputted to a second input of the motion vector detecting circuit
405
a
. An output of the motion vector detecting circuit
405
a
is inputted to a prediction mode selector
406
. In the meantime, the reference picture outputted from the frame memory
404
b
is given to a first input of a motion vector detecting circuit
405
b
. The video signal
321
inputted from the input terminal
401
b
is given to a second input of the motion vector detecting circuit
405
b
. The output of the motion vector detecting circuit
405
b
is given to the second input of the prediction mode selector
406
. The video signal
321
inputted from the input terminal
401
b
is given to a third input of the prediction mode selector
406
. A zero signal is given to a second input of a switch
407
. A second output of the prediction mode selector
406
is given to a third input of the switch
407
. The output
323
of the switch
407
is outputted from a output terminal
402
.
FIG. 4
is a block circuit diagram showing an inside structure of the data extending circuit
217
in FIG.
1
. In
FIG. 4
, the video signal inputted from the frame sector inverse converting circuit
216
is inputted to a reception buffer
501
. An output from the reception buffer
501
is inputted to a variable-length decoder
502
, and the output therefrom is inversely quantized at an inverse quantizer
503
. Then, the output is subjected to an inverse discrete cosine transform at an inverse DCT circuit
504
. The output is provided as a first input of an adder
506
. In the meantime, the output of the reception buffer
501
is provided as a prediction data decoding circuit
505
while an output of the prediction data decoding circuit
505
is provided as a second output of the adder
506
. The output of the adder
506
is outputted to the D/A converter
218
via a memory circuit
507
.
Next, operation of the device of
FIG. 1
will be explained. As one high efficiency coding mode in the case of coding a video signal, there is an coding algorithm for a MPEG (Moving Picture Expert Group) mode. This is a hybrid coding mode which combines an inter-frame prediction coding using a motion compensation prediction and an intra-frame conversion coding. This conventional example uses a data compressing circuit
202
having a structure shown in FIG.
2
and adopts the aforementioned MPEG mode.
FIG. 5
shows a simplified data arrangement structure (layer structure) of MPEG mode. In
FIG. 5
, reference numeral
621
denotes a sequence layer comprising a group of pictures (hereinafter referred to as “GOP”) comprising a plurality of frame data items,
622
a GOP layer comprising several pictures (screens),
623
a slice which divides one screen into several blocks,
624
a slice layer which has several macroblocks,
625
a macroblock layer,
626
a block layer which includes 8 pixels×8 pixels.
This macroblock layer
625
is a block which includes a least unit of 8 pixels×8 pixels, for example, in the MPEG mode. This block is a unit for performing DCT. At this time, a total of 6 blocks, including adjacent four Y signal blocks, one Cb block which corresponds to the Y signal blocks in position, and one Cr block are referred to as macroblock. A plurality of these macroblocks constitute a slice. In addition, the macroblocks constitute a minimum unit of a motion compensation prediction, and a motion vector for the motion compensation prediction is formed in macroblock units.
Subsequently, a process for the inter-frame prediction coding will be explained.
FIG. 6
shows an outline of the inter-frame prediction coding. Pictures are divided into three types, namely an intra-frame coded picture (hereinafter referred to as an I picture), a one direction prediction coded picture (hereinafter referred to as a P picture), and a both direction prediction coded picture (hereinafter referred to as a B picture).
For example, in the case where one picture out of N pictures is set as an I pic
Asamura Yoshinori
Hatano Yoshiko
Ishida Yoshinobu
Kasezawa Tadashi
Kurahashi Satoshi
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