Digital video encoder for digital video system

Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal

Reexamination Certificate

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Details

C348S608000

Reexamination Certificate

active

06285717

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a digital video system such as a multi media system, a digital video, a digital video disk (DVD), a video-CD, a digital VCR, a digital television, a camcorder and a video editor, and more particularly, to a digital video encoder in a digital video system.
A digital video decoder in a digital video system reads compressed data from a storage medium and decodes it to thus output a decoded digital video signal. In a digital video encoder, the decoded digital video signal is input, and divided into chrominance and luminance signals. The divided signals are converted to an analogue composite video baseband signal (CVBS) in response to a clock, a vertical synchronizing signal, a horizontal synchronizing signal, and a field signal. This CVBS has analogue video data and is transmitted to a display device such as a CRT.
In a conventional digital video encoder of a digital video system, a main clock is generated from a signal having 4fsc (Here, fsc is 3.58 MHz in NTSC or 4.43 MHz in PAL). Thus, according to the data communication regulation CCIR (International Radio Consultative Committee)
601
or
656
, a standard data sampling clock frequency used in the conventional digital video encoder should be 27 MHz or 13.5 MHz. Thus, when using the conventional digital video encoder, input digital video data is not synchronized with the main clock and thus the data can be damaged.
In particular, when the digital data compressed according to an MPEG standard is restored and displayed, a blocking phenomenon can be generated due to a nonlinear feature of data according to the connection between scanning lines.
Also, when compressing the data using the MPEG standard, a high-frequency data component is removed so that a gentle noise, that is, mosquito noise is generated on a display screen when reproducing the compressed data.
Furthermore, since a chip for an on screen display (OSD) and a chip serving as a digital video encoder are separately provided in the prior art, a clock corresponding to each chip should be separately generated and various financial and spacial problems occur when connecting one chip to the other in the case of requesting an OSD and a digital video encoder simultaneously.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a digital video encoder for a digital video system wherein digital video data compressed using an MPEG standard is synchronized with one of the main clocks using two main clocks.
It is another object of the present invention to provide a digital video encoder for a digital video system wherein a mosquito noise and a blocking phenomenon are not generated.
It is still another object of the present invention to provide a digital video encoder for a digital video system having an on screen display function.
To accomplish the first object, there is provided a digital video encoder for a digital video system wherein the encoder receives digital video data output from an MPEG decoder and outputs an analogue composite video baseband signal, comprising: first selection means for selectively outputting first and second clocks in response to a first selection signal; signal dividing means for dividing the input digital video data into a luminance signal and a chrominance signal in response to the output of the first selection means; luminance signal processing means for regulating the gain and offset of the luminance signal, adding a synchronizing signal to the regulated luminance signal, and filtering a low band component of the luminance signal to output the filtered signal as a digital luminance signal; chrominance signal processing means for regulating the gain of the chrominance signal, interpolating the gain-regulated chrominance signal, producing color difference signals, interpolating the produced color difference signals, filtering a low band component of the interpolated color difference signals, and modulating the filtered color difference signals, to thereby output the modulated signal as a digital chrominance signal; signal synthesizing means for synthesizing the digital luminance and chrominance signals and outputting the synthesized signal; first digital-to-analogue converting means for converting the synthesized signal to an analogue signal and outputting the converted signal as the analogue composite video baseband signal; and controlling means for outputting the first selection signal corresponding to the size and input speed of the input digital video signal.
To accomplish the second object, it is preferable that the digital video encoder for a digital video system further comprises: line information storage means for receiving the luminance and chrominance signals output from the signal dividing means and storing line information of the respective signals; line comparing means for comparing the line information stored in the line information storage means with currently-input line information and outputting the compared result; and line information producing means for producing new line information according to the compared result and outputting the new line information as the luminance and chrominance signals to the luminance and chrominance signal processing means, respectively.
To accomplish the third object, it is preferable that the digital video encoder for a digital video system further comprises on-screen display means for outputting luminance and chrominance components of stored data to be displayed on screen and mapping data corresponding to a mapping address input from the controlling means to the luminance and chrominance processing means, respectively.


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Teichner, D., “PAL encoding and decoding with improved luminance/chrominance separation”, IEE 1988 International Conference on Consumer Electronics.

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