Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-09-28
2003-06-03
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S032000, C326S034000
Reexamination Certificate
active
06573747
ABSTRACT:
FIELD
The present invention is directed to adaptive impedance control of input/output circuits. More particularly, the present invention is directed to update schemes for adaptive impedance control of input/output circuits.
BACKGROUND
If an input/output (I/O) data signal experiences any discontinuity (e.g., change in impedance) during transfer, such signal can experience undesirable effects such as signal reflection.
FIG. 1
shows a first integrated circuit (IC) numbered IC
A
, a second IC numbered IC
B
, and a plurality of transmission lines IL
N−1
, IL
N
, IL
N+1
connected to I/O terminals and providing signal transmission paths therebetween, with the illustration of “
” indicating that there may be many more (e.g., hundreds of) I/O terminals and transmission lines interconnected therebetween. A I/O terminal may include a pad cell containing a driver/receiver circuit composed of, for example, a pair of connected inverters (not shown) or it may include some other arrangement of elements. Also, the transmission lines IL
N−1
, IL
N
, IL
N+1
may be connected to a characteristic external impedance R
ext
, of, for example, 50 ohms (Ù). If IC
A
outputs a signal SIG from an I/O terminal onto transmission line IL
N−1
, such signal SIG will travel along transmission line IL
N−1
, and unless the impedance of an I/O terminal of IC
B
is matched, such traveling signal will experience discontinuity and will experience undesirable effects such as a signal reflection REFL. Such reflection REFL is undesirable because it lessens a signal strength of the signal SIG which is actually inputted into IC
B
, and travels back to IC
A
. It may then reflect back from IC
B
if it is not matched to the transmission line impedance, and this reflection may interfere with subsequent signal reception at IC
B
and with the edge rate (slew rate) of the data signal.
IC manufacturing processes vary substantially from manufacturing lot to manufacturing lot, and as a result of such manufacturing variations, IC components correspondingly vary making it very difficult and/or cost prohibitive to match impedances with high precision at the time of manufacture. Further, even if such precision could be provided at the time of manufacture, such approach would still be disadvantageous insofar as it does not allow for adjustment to varying transmission lines, and for continuous voltage and temperature compensations. That is, voltage and temperature environments, for example, within an IC and/or on signal transmission lines change over time during the operation of an apparatus. Accordingly, adaptive impedance control circuits can be provided on the die of an IC which “continuously” adapt to such changes over time in order to match impedances and thus control reflections and the edge rate of the data signal transferred across a transmission line. With such on-die impedance matching, little discontinuity and minimal reflections are experienced by the data signal at the end of the transmission line.
There are various update schemes for such adaptive impedance control circuits. Update schemes may, for example, either put the bus on hold or issue a special transaction on the I/O to do an update or simply decode all the 4 bits and do a linear or gray code update to prevent glitches on the bus. Thermometer coded bits may be used for both pullup and pulldown impedance control. This requires a lot of routing channels to all the pad cells. An asynchronous updating scheme cannot be used for this pulldown driver since it will cause output timing pushout if the update occurs during data transition. A driver idle update scheme may update the controlled impedance when the bus is idle. This approach has the disadvantage that the update may never happen within the time delay of the impedance drift due to temperature or voltage changes.
A complicated scheme may be used to do the pulldown impedance update in which, not only are the thermometer bits distributed to each pad cell, there are two control bits distributed to each pad cell. These two bits indicate when the actual update is done on the pulldown. The delay for these two bits is decided by the control bits from the frequency governor which changes the delay depending on the bus clock ratio.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 5095231 (1992-03-01), Sartori et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5559447 (1996-09-01), Rees
patent: 5677639 (1997-10-01), Masiewicz
patent: 5955894 (1999-09-01), Vishwanthaiah et al.
patent: 6049221 (2000-04-01), Ishibashi et al.
patent: 6114898 (2000-09-01), Okayasu
Antonelli Terry Stout & Kraus LLP
Tokar Michael
Tran Anh Q.
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