Digital to analog converter including a ferroelectric...

Static information storage and retrieval – Systems using particular element – Ferroelectric

Reexamination Certificate

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C365S051000, C365S063000

Reexamination Certificate

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06754095

ABSTRACT:

CROSS REFERENCES TO RELATED APPLICATIONS
The present invention claims priority to its priority document No. 2001-334360 filed in the Japanese Patent Office on Oct. 31, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital to analog converter comprising a ferroelectric non-volatile semiconductor memory (so-called FERAMS), and to a method of converting digital data to analog data using the digital to analog converter above.
2. Description of the Related Art
There are various known digital to analog converters (hereinafter abbreviated as D/A converters) such as those using a load resistor, or a ladder resistor network, and those which obtain analog output by converting digital input into a pulse number or pulse width and passing it through a low-pass filter.
In general, these conventional D/A converters do not have memory functions. Therefore, it is difficult for a conventional D/A converter by itself to temporally control the outputting of the converted analog data, and in order to retain or edit the converted analog data, a separate device or storage medium is required. In addition, in converting a large volume of digital data, a high-speed D/A converter is required, and converting a large volume of digital data to analog data is thus difficult.
SUMMARY OF THE INVENTION
Therefore, one aspect of the present invention is to provide a novel digital to analog converter which, in the conversion of digital data to analog data, enables temporal controlling of the outputting of the converted analog data, and/or which enables high-speed conversion of a large volume of digital data to analog data, and is also to provide a method for converting digital data to analog data using such a digital to analog converter.
A digital to analog converter according to a first aspect of the present invention is a digital to analog converter including a ferroelectric non-volatile semiconductor memory, wherein
the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line; and
(B) N (where N≧2) memory units;
each of the memory unit comprises:
(B-1) a selection transistor;
(B-2) a memory cell comprising a first electrode, a ferroelectric layer and a second electrode; and
(B-3) a plate line;
wherein the first electrode is connected to the data line via the selection transistor,
the second electrode is connected to the plate line, and
the area of the ferroelectric layer of the individual memory cells differs among the memory cells.
A digital to analog converter according to a second aspect of the present invention is a digital to analog converter comprising a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) a memory unit comprising M (where M≧2) memory cells; and
(C) M plate lines,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
the first electrode of the memory cells is shared in the memory unit and is connected to the data line,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the memory unit is connected to the mth plate line, and
the area of the ferroelectric layer of the individual memory cells differs among the memory cells.
A digital to analog converter according to a third aspect of the present invention is a digital to analog converter including a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) N (where N≧2) memory units individually comprising M (where M≧2) memory cells; and
(C) M×N plate lines;
wherein the N memory units are layered with an insulation layer in between each,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each memory unit, the first electrode of the memory cell is shared, and is connected to the data line,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the memory unit of the nth (where n=1, 2, . . . N) layer is connected to the [(n−1)M+m]th plate line, and
the area of the ferroelectric layer of the memory cells differs among the memory cells.
A digital to analog converter according to a fourth aspect of the present invention is a digital to analog converter including a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line;
(B) N (where N≧2) selection transistors;
(C) N memory units each comprising M (where M≧2) memory cells; and
(D) M plate lines;
wherein each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each of the memory units, the first electrode of the memory cells is shared,
the shared first electrode of the nth (where n=1, 2, . . . N) memory unit is connected to the data line via the nth selection transistor,
in the nth memory unit, the second electrode of the mth (where m=1, 2, . . . M) memory cell is connected to the mth plate line which is shared between the memory units, and
the area of the ferroelectric layer of the memory cells in each of the memory units differs among the memory cells.
A digital to analog converter according to a fifth aspect of the present invention is a digital to analog converter comprising a ferroelectric non-volatile semiconductor memory,
wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) N (where N≧2) data lines;
(B) N selection transistors;
(C) N memory units each comprising M (where M≧2) memory cells; and
(D) M plate lines;
N memory units are layered with an insulation layer in between each,
each of the memory cells comprises a first electrode, a ferroelectric layer and a second electrode,
in each of the memory units, the first electrode of the memory cells is shared,
the shared first electrode in the memory unit of the nth (where n=1, 2, . . . N) layer is connected to the nth data line via the nth selection transistor,
the second electrode of the mth (where m=1, 2, . . . M) memory cell in the memory unit of the nth layer is connected to the mth plate line which is shared between the memory units, and
the area of the ferroelectric layer of the memory cells in each of the memory units differs among the memory cells.
A method for converting digital data to analog data according to the first aspect of the present invention is a method for converting a digital data of M bits to analog data using a digital to analog converter including a ferroelectric non-volatile semiconductor memory, wherein the ferroelectric non-volatile semiconductor memory comprises:
(A) a data line; and
(B) N (where N≧2) memory units;
each of the memory units comprises:
(B-1) a selection transistor;
(B-2) a memory cell comprising a first electrode, a ferroelectric layer and a second electrode; and
(B-3) a plate line;
the first electrode is connected to the data line via the selection transistor,
the second electrode is connected to the plate line, and
the area of the ferroelectric layer of the individual memory cells differs among the memory cells, and
the method comprises the steps of:
setting the selection transistor to a conductive condition and driving the data line and the plate line to write the mth binary data (where m=1, 2, . . . M) in the memory cells of the mth memory unit;
setting the selection transistor to a conductive condition, and driving all plate lines to simultaneously read out data from the memory cells in all of the memory units; and
outputting the resultant electric potential which is generated across the data line.
A method for converting digital data to analog data according to the second aspect of the present invention is a method for converting M bits of digital data to analog data using a digital to analog converter,
wherein the digital to analog converter includes a ferroelectric non-volatile semiconductor memory,
the ferr

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