Digital timing recovery method for communication receivers

Details Digital timing recovery method for communication receivers Digital timing recovery method for communication receivers

2006-01-03

2006-01-03

Phu, Phuong (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S376000, C375S371000

Reexamination Certificate

active

06983032

ABSTRACT:
The present invention provides an apparatus, system and method for synchronizing a local clock signal with a remote clock signal in a communication network. Phase information is used to calculate a number of “clock jitters” per unit of time needed to synchronize the locally generated clock with the remote clock. Introducing (removing) a given amount of delay at a particular point in the local clock signal results in a positive (negative) jitter in which its minimum value defines the jitter resolution. The jitters are introduced to the local clock signal from a plurality of tapped delay line elements (310) selected by a phase selector (350) in response to a timing correction signal issued by a phase error module (520).

REFERENCES:
patent: 5646968 (1997-07-01), Kovacs et al.
patent: 5771264 (1998-06-01), Lane
patent: 6353648 (2002-03-01), Suzuki
patent: 6389091 (2002-05-01), Yamaguchi et al.
patent: 6788754 (2004-09-01), Liepe

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