Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Multiple or variable intervals or frequencies
Reexamination Certificate
2000-07-14
2004-06-15
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Multiple or variable intervals or frequencies
C713S401000, C713S503000
Reexamination Certificate
active
06751745
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital synchronization circuit for generating an output clock signal which is in synchronization with a phase of an input data signal.
2. Description of the Background Art
A method of implementing a synchronization circuit for generating an output clock signal which is in synchronization with a phase of an input data signal serially transmitted from an external portion of a chip is disclosed in
IEEE JOURNAL OF SOLID
-
STATE CIRCUITS,
Vol. 25, No. 6,DECEMBER 1990, pp. 1385-1394, B. Kim, D. N. Helman and P. Gray, “A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-&mgr;m CMOS.”
Disclosed in the reference is a method of generating a desired clock signal by using a polyphase clock signal generated by a voltage controlled oscillator (hereinafter abbreviated as a VCO) including inverter columns connected in a ring like form and whose delay times are controllable.
A polyphase clock generation circuit generating the polyphase clock signal has a PLL (phase locked loop) structure which is controlled such that an oscillation frequency of the VCO is the same as an operation frequency of the input data signal which is input from the external portion of the chip. The signals are separately transmitted from nodes of inverter columns connected in the ring like form in the VCO, so that a plurality of clock signals having different phases but the same phase difference, i.e., polyphase clock signals, are output.
Referring to
FIG. 14
, a conventional digital synchronization circuit
9000
using polyphase clock signals will be described.
Conventional digital synchronization circuit
9000
includes: a polyphase clock generation circuit
910
outputting clock signals CLK
1
-CLKn to n signal lines; n-bit latch circuits
920
and
930
; a clock phase determination circuit
950
; and a selector
960
selecting and outputting one of n clock signals CLK
1
to CLKn.
Latch circuit
920
includes n D type flip-flops FF
1
to FFn. Flip-flops FFi (i=1 to n) is arranged in correspondence with clock signal CLKi.
Next, an arrangement of conventional digital synchronization circuit
9000
will be described. Clock signals CLK
1
to CLKn are respectively connected to clock input terminals of flip-flops FF
1
to FFn and the first to nth data input terminals of selector
960
. Input data signals DIN are applied to all of data input terminals D of flip-flops FF
1
to FFn.
Further, output signals from flip-flops FF
1
to FFn are respectively applied to the first to the nth bit data input terminals of latch circuit
30
. Clock signal CLKn is applied to the clock input terminal of latch circuit
930
.
The n-bit output signal output from latch circuit
930
is applied to the input terminal of clock phase determination circuit
950
.
A clock selection signal CSL from clock phase determination circuit
950
is applied to a control input terminal of selector
960
, and an output clock signal OUTCLK is output from an output terminal of selector
960
.
Now, an operation of conventional digital synchronization circuit
9000
will be described.
Clock signals CLK
1
to CLKn having different phases and having the same frequency as that of input data signal DIN are output from polyphase clock generation circuit
910
. Input data signals DIN are respective latched at flip-flops FF
1
to FFn by clock signals CLK
1
to CLKn. More specifically, input data signals DIN are sampled by clock signals CLK
1
to CLKn, and the sampled data are retained in flip-flops FF
1
to FFn.
The sampled data in FF
1
to FFn are received by latch circuit
930
in the next stage by clock signal CLKn.
The n-bit data in latch circuit
930
is applied to clock phase determination circuit
950
.
Here, clock phase determination circuit
950
determines the change in potential level of the signal which has been obtained by sampling input data signal DIN in time series, so that a clock selection signal CSL for selecting one of clock signals CLK
1
to CLKn is output as a suitable clock signal for correctly sampling input data signal DIN.
Selector
960
selects one of clock signals CLK
1
to CLKn in accordance with a value of dock selection signal CSL. The selected signal is output as output clock signal OUTCLK.
As described above, digital synchronization circuit
9000
selects one of clock signals CLK
1
to CLKn having a phase in synchronization with input data signal DIN for outputting the selected signal as output clock signal OUTCLK. Thus, the synchronization circuit by digital control is achieved.
In the case of a digital synchronization circuit selecting one of clock signals CLK
1
to CLKn by selector
960
for outputting the selected signal as output clock signal OUTCLK in synchronization with input data signal DIN, a hazard, which is an undesirable change in potential level of a signal in a short period of time, may be caused to output clock signal OUTCLK in switching clock signals at a certain transition timing of clock selection signal CSL.
The hazard caused to output clock signal OUTCLK will be described with reference to FIG.
15
.
Assume that, at a time t
100
, the clock signal selected by selector
960
in accordance with the value of clock selection signal CSL switches from clock signal CLKc to CLKc+1. Further, assume that potentials of clock signals CLKc and CLKc+1 are both at an “H” level. Here, c=1, 1<c <n−2 (c: integer) or c=n−2.
At the time, potentials of clock signals CLKc and CLKc+1 are both at the “H” level, so that even if the signal selected by selector
960
is switched, no hazard is caused to output clock signal OUTCLK.
Next, at a time t
101
, assume that the clock signal selected by selector
960
in accordance with the value of clock selection signal CSL switches from clock signal CLKc+1 to CLKc+2. Further, assume that the potential level of clock signal CLKc+1 changes from an “L” level to the “H” level shortly before time t
101
, and the potential level of clock signal CLKc+2 changes from the “L” to “H” level shortly after time t
101
.
Then, the potential level of output clock signal OUTCLK from selector
960
changes from the “L” to “H” level shortly before time t
101
, then to the “L” level at t
101
, and further to “H” level shortly after the t
101
.
More specifically, a hazard is caused to the potential of output clock signal OUTCLK, that is characterized by undesirable changes in potential level in a short period of time.
The hazard caused to output clock signal OUTCLK would adversely affect the operation of the external circuit receiving output clock signal OUTCLK.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a digital synchronization circuit capable of outputting an output clock signal which is stably in synchronization with an input data signal without causing a hazard.
The digital synchronization circuit according to one aspect of the present invention includes: a clock generation circuit generating a plurality of clock signals having substantially the same frequency and having different phases; a selection circuit selectively outputting corresponding one having plurality of clock signals in accordance with a first selection signal; a clock determination circuit sampling the input data signal using the plurality of clock signals and selecting one of the plurality of clock signals based on the sampling result for outputting a second selection signal indicating the selection result; and a selection control circuit adjusting a timing at which the second selection circuit changes and outputting the first selection signal. The selection control circuit changes a value of the first selection signal from a first value to a second value in a period in which potentials of clock signals represented by the first and second values match in response to the change in value of the second selection signal from the first value to the second value.
Preferably, the selection control circuit includes: a clock selection circuit selectiv
Kondoh Harufusa
Nishida Koichi
Yoshimura Tsutomo
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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