Digital storage element architecture comprising dual scan...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Details

C327S218000

Reexamination Certificate

active

07375567

ABSTRACT:
A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to electrical ground. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to electrical ground. When a clock signal is in a first state, the first single transistor is activated to preset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to preset the digital storage element.

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patent: 2005/0091562 (2005-04-01), Krishnamoorthy et al.
Khan, Waheed U. et al., U.S. Appl. No. 10/952,289, filed Sep. 28, 2004, entitled, “High Speed Energy Conserving Scan Architecture,” 18 pages including 4 pages of Formal Drawings.

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