Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-05-26
2001-05-29
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S171000, C711S172000
Reexamination Certificate
active
06240497
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory system included in a digital signal processor or the like.
2. Description of the Related Art
Generally, in a digital signal processor, separate memory spaces are provided for programs and data. Sometimes, however, program memory space runs short, and excess data memory space exists, and it would be desirable to be able to reallocate memory from one to the other. Typically, however, the memory space is completely divided into a program space and a data space. That is, a program memory is connected to only a data bus. Thus, since the program memory and the data memory are completely independent of each other, there is no way to use part of the program memory data memory and vice versa.
In order to permit reallocation between the program memory and the data memory, in one digital signal processor design, the system includes a program bus, a data bus, a large scale memory space and a memory priority sequence controller, so that the user can freely allocate the memory space between the memory spaces for the program bus and the data bus as required. A system of this kind is shown in Japan patent application 63-303452, published Dec. 12, 1988.
In the above-described prior art memory system, however, the program bus has the same bit width as the data bus. However, in some digital signal processors such as the PD7701X family manufactured by NEC Corporation, a program memory having a bit width of 32 bits and two data memories each having a bit width of 16 bits are provided. That is, a program memory space and two data memory spaces are provided. The two data memory spaces are helpful in carrying out pipeline processing Because the program bus and the data bus in these digital signal processors have different bit widths, the memory management scheme shown in Japan published application 63-303452 can not be used. If additional data or program memory is needed, the onboard memory must be increased, or external memory must be provided, which increases the manufacturing cost. In addition, the memory priority sequence controller in the published application dissipates a large amount of power.
SUMMARY OF THE INVENTION
It is an object of the present invention to improve the adaptability of memory space in a memory system including a program memory and at least two data memories having a different bit width from the program memory.
According to the present invention, in a memory system, a plurality of memories having different bit widths from each other and each including at least one memory block and a plurality of buses are provided. At least one selector is connected between the block and at least two of the buses and selectively connects the block to one of the at least the buses.
The selector freely allocates the memory spaces of the memories, thus substantially increasing the memory capacity. In addition, the selector dissipates hardly any power.
REFERENCES:
patent: 5584010 (1996-12-01), Kawai et al.
patent: 5630099 (1997-05-01), MacDonald et al.
patent: 5799138 (1998-08-01), Yoshida
patent: 5819054 (1998-10-01), Ninomiya et al.
patent: 5862396 (1999-01-01), Motomura
patent: 5909557 (1999-06-01), Betker et al.
Chace C. P.
Kim Matthew
NEC Corporation
Ostrolenk Faber Gerb & Soffen, LLP
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