Digital signal processor having an on-chip pipelined EEPROM data

Details Digital signal processor having an on-chip pipelined EEPROM data Digital signal processor having an on-chip pipelined EEPROM data

1999-02-01

2000-01-04

Mai, Son

Static information storage and retrieval

Floating gate

Particular biasing

36518511, 36523005, G11C 1606

Patent

active

060117192

ABSTRACT:
A nonvolatile memory architecture (10) contains a plurality of memory arrays (12) formed by a plurality of floating gate memory cells and supports a 1.times. and 2.times. architecture. The nonvolatile memory design contains high voltage row decoders (16), low voltage row decoders (18), data multiplexors (24) and low voltage control circuitry (22). The nonvolatile memory architecture (10) features a pipelined scheme with a 100 MHz operation. Data multiplexers (24) and sense amplifier circuitry (26) with a master/slave portion increase the data access rate.

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