Fully integrable phase locked loop with low jitter

Details Fully integrable phase locked loop with low jitter Fully integrable phase locked loop with low jitter

1996-03-06

1997-08-05

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 25, H03L 7099, H03L 7107

Patent

active

056546750

ABSTRACT:
A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.

REFERENCES:
patent: 5319320 (1994-06-01), Abe et al.
patent: 5369376 (1994-11-01), Leblebicioglu
patent: 5495512 (1996-02-01), Kovacs et al.
Proceedings of the IEEE 1992 Custom Integrated Circuits Conference, May 3, 1992, Boston, pp. 24.2.1-24.2.5. Reza Shariadoust, et al. "A Low Jitter 5 MHz to 180 MHz Clock Synthesizer for Video Graphics".

Affiliated with

Also associated with

Rating

Fully integrable phase locked loop with low jitter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Fully integrable phase locked loop with low jitter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Fully integrable phase locked loop with low jitter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1077618