Electrical computers and digital processing systems: processing – Processing control – Instruction modification based on condition
Reexamination Certificate
1999-06-29
2002-07-30
Ellis, Richard L. (Department: 2651)
Electrical computers and digital processing systems: processing
Processing control
Instruction modification based on condition
C712S205000, C712S234000
Reexamination Certificate
active
06427205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a digital signal processor and a processor, and more particularly to a digital signal processor and a processor improved toward a decrease of processing instructions during execution of conditional instructions.
2. Description of the Prior Art
Processing by a digital signal processor (hereinafter called DSP) is pipeline-controlled, and it is divided into three steps, namely, fetching of an instruction, decoding of the instruction and execution of the instruction for instance. An example of pipeline processing made up of these three steps is shown in FIG.
4
.
As shown in
FIG. 4
, in pipeline processing of DSP, fetching, decoding and execution of an instruction progress in parallel. That is, when fetching of an instruction N is completed, the instruction N is decoded, and a next instruction N+1 is fetched concurrently. Then, the instruction N is executed, instruction N+1 is decoded, and a still next instruction N+2 is fetched. In this manner, by dividing processing of every single instruction into three steps, processing of instructions is repeated sequentially.
For executing such pipeline processing, it was the problem that one cycle had to be skipped before a condition execution instruction. That is, an instruction other than “condition generation instruction or condition execution instruction” had to be inserted before the condition execution instruction. In other words, an instruction not changing the condition flag and other than the condition execution instruction had to be inserted. Grounds of this problem is explained below in detail with reference to
FIGS. 5 through 7
.
FIG. 5
is a diagram showing a hardware construction of DSP for transferring contents of a register A to a register B under a condition by using such a pipeline processing function.
FIG. 6
is a timing chart in case of the condition being consistent.
FIG. 7
is a timing chart in case of the condition being inconsistent.
As shown in
FIG. 5
, a program counter is supplied to instruction memory
100
. Based on a value of the program counter, an instruction is read and introduced into an instruction register
102
in an instruction fetch cycle. The instruction taken into the instruction register
102
is decoded by an instruction decoder
104
in an instruction decode cycle. The instruction decoder
104
is supplied with a condition flag Z from a condition judge block
106
. The instruction decoder
104
decodes the condition flag Z as well upon decoding the instruction from the instruction register
102
. Therefore, the content of the condition flag Z has to be fixed before decoding the instruction. In accordance with the content of the condition flag Z, that is, depending on whether the condition is consistent or not, a signal is output to a gate
108
of the register A. That is, when the condition is consistent, an enable signal is output to the gate
108
. When the condition is not consistent, the enable signal is not output to the gate
108
. Therefore, when the condition is inconsistent, the value of the register A does not ride on the data bus. When the condition is consistent, a B register clock is supplied to a register B from an OR circuit
110
, and the content of the register A is taken into the register B. In contrast, when the condition is inconsistent, no B register clock signal is supplied to the B register from the OR circuit
110
, and the content of the register A is not taken into the register B.
Next explained is an operation timing in case of consistency of the condition with reference to FIG.
6
. Instruction N is an instruction for generating a condition, with which the flag Z becomes 1 or 0 in accordance with the result of an operation instruction, for example. Instruction N+1 is an instruction other than “condition generation instruction or condition execution instruction”, which does not change the flag Z and which is other than condition execution instruction. Typically, “No Operation” instruction which instructs nothing be executed is inserted. Instruction N+2 is a condition execution instruction which instructs execution of the instruction only under a certain result of the instruction N. For example, it is such as “if Z=0 then B=A”.
As will be understood from
FIG. 6
, instruction N for generating a condition is fetched in a clock cycle T
1
. In the next clock cycle T
2
, instruction N is decoded, and instruction N+1 other than “condition generation instruction or condition execution instruction” is fetched simultaneously. In the next clock cycle T
3
, instruction N is executed, and the condition flag Z rises upon the rising edge of the register clock. In the clock cycle T
3
, instruction N+1 is decoded simultaneously. However, since the condition flag Z does not rise during decoding, the proper content is not obtained yet even by decoding the condition execution instruction. Therefore, instruction N+1 other than “condition generation instruction or condition execution instruction” has to be inserted. In the clock cycle T
3
, instruction N+2 which is condition execution instruction is fetched concurrently.
In the clock cycle T
4
, instruction N+2 is decoded. In the clock cycle T
4
, since execution of the instruction N for generating a condition is already completed, the condition flag Z is up. Therefore, condition execution instruction N+2 meets with the condition flag Z, proper decoding is executed. That is, in the example of
FIG. 6
on a case with the condition being consistent, decoding is executed to replace the register B with the register A. As a result, the value of the register A rides on the data bus at the rising edge of the register clock, and the B register clock enable changes from HIGH to LOW.
In the clock cycle T
5
, condition execution instruction N+2 is executed. That is, the B register clock is input to the register B, and the value on the data bus is taken into the B register at the rising edge of the B register clock. In the next clock cycle T
6
, et seq., the value of the register B maintains the value of the register A taken last.
Next explained is an operation timing of a case where the condition is inconsistent. As shown in
FIG. 7
, the sequence progresses in the same manner as the case with the condition being consistent up to the clock cycle T
3
. Therefore, also in the clock cycle T
4
, et seq., the condition flag Z keeps down. B register clock enable keeps HIGH. As a result, no B register clock is supplied to the B register.
In the clock cycle T
4
, condition execution instruction N+2 is decoded. During the decoding process, the condition flag Z is decoded together. In this case, since the condition is inconsistent, it is necessary to prevent replacement of the register B by the content of the register A. For this purpose, condition execution instruction is changed to “No Operation” instruction upon decoding. Therefore, the content of the register A does not ride on the data bus in the clock cycle T
5
. Additionally, since no B register clock is input to the B register, the content of the register B is not changed. Also in the clock cycle T
6
, the content of the register B is not changed.
As explained above, conventional techniques involved the constraint that one cycle had to be skipped before a condition execution instruction. That is, since it was necessary to complete execution of a condition generation instruction and fix the content of the condition flag Z upon decoding a condition execution instruction, there was the constraint that an instruction other than “condition generation instruction or condition execution instruction” had to be inserted between an instruction for generating a condition and a condition execution instruction. The requirement to insert a redundant instruction which is an instruction other than “condition generation instruction or condition execution instruction” was one of factors increasing useless processes. Especially when a program containing such in
Furusawa Toshiyuki
Mori Koichi
Sonoda Daisuke
Ellis Richard L.
Patel Gautam R.
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