Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output command process
Reexamination Certificate
1999-10-15
2002-08-27
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output command process
C710S004000, C710S020000, C710S035000, C710S039000, C710S052000, C710S056000, C710S069000, C710S308000
Reexamination Certificate
active
06442622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital signal processor which is suitable for use in modems or the like, and a method of processing digital signals.
2. Prior Art
Many modems (modulator and demodulators) have a function of changing the sampling frequency of a transmission signal transmitted by a communication network in accordance with the status of the communication network to which they are connected. DSPs (digital signal processors) installed in modems of this kind are required to have a function of changing the sampling frequency of input sampled data, and are therefore generally equipped with oversampling filters and decimation filters, in addition to band pass filters.
Digital filters such as oversampling filters and decimation filters are all constructed such that input sampled data to be processed are once stored in a memory and the stored sampled data are read from the memory. The manner of storing and reading the sampled data is, however, different between the oversampling filters and the decimation filters, i.e. depending upon the kind of signal processing. More specifically, for example, an oversampling filter is constructed such that one piece of sampled data is stored in a memory and a plurality of sampled data are read from the memory during one sampling period, whereas a decimation filter is constructed such that a plurality of sampled data are stored in a memory and one piece of sampled data is read from the memory during one sampling period.
Since the manner of storing and reading the sampled data with respect to the memory is thus different depending upon the kind of signal processing, it is generally difficult to store sampled data corresponding to plural kinds of signal processing in a common memory. Therefore, conventionally, memories and access control means therefor are provided, respectively, for plural kinds of signal processing, such that sampled data is stored in a memory exclusively provided for each kind of signal processing. This, however, necessitates the use of an increased amount of hardware in the DSP.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a digital signal processor and a digital signal processing method which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing.
To attain the above object, the present invention provides a digital signal processor comprising a storage device that stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing, a counter that updates a count value thereof every sampling period and generates the updated count value as a basic address, and a sampled data input and output device that performs an input and output operation every sampling period, the input and output operation comprising generating plural kinds of offset addresses corresponding, respectively, to the plural kinds of signal processing and not overlapping with each other, generating at least one write address or read address for the sampled data for each of the plural kinds of signal processing by modifying the basic address by at least one of the offset addresses corresponding to each of the plural kinds of signal processing, and delivering the generated at least one write address or read address to the storage device.
In a preferred form of the invention, the plural kinds of signal processing include at least one kind of signal processing which includes a process of storing a plurality of sampled data in the storage device or reading a plurality of sampled data from the storage device every sampling period, the sampled data input and output device performing the input and output operation every sampling period, the input and output operation comprising generating a plurality of offset addresses corresponding to the at least one kind of signal processing, generating a plurality of write addresses or read addresses for the sampled data for the at least one kind of signal processing by modifying the basic address by the plurality of offset addresses, and delivering the generated plurality of write addresses or read addresses to the storage device.
In a preferred embodiment of the invention, the plural kinds of signal processing include 1/M-fold decimation processing which includes a process of storing M pieces of sampled data (M is an integer) in the storage device and reading one piece of sampled data from the storage device every sampling period, the sampled data input and output device performing an input and output operation every sampling period, the input and output operation comprising generating M offset addresses for writing corresponding to said 1/M-fold decimation processing, generating M write addresses which differ from each other by modifying the basic address by the M offset addresses for writing, delivering the generated M write addresses to the storage device, generating one offset address for reading corresponding to the 1/M-fold decimation processing, generating one read address by modifying the basic address by the one offset address for reading, and delivering the generated one read address to the storage device.
Further, in a preferred embodiment of the invention, the plural kinds of signal processing include K-times oversampling processing which includes a process of storing one piece of sampled data in the storage device and reading J pieces of sampled data (J is an integer) from the storage device K times (K is an integer) every sampling period, the sampled data input and output device performing an input and output operation every sampling period, the input and output operation comprising generating M offset addresses for writing corresponding to the 1/M-fold decimation processing, generating M write addresses which differ from each other by modifying the basic address by the M offset addresses for writing, delivering the generated M write addresses to the storage device, generating one offset address for reading corresponding to the
1
/M-fold decimation processing, generating one read address by modifying the basic address by the one offset address for reading, and delivering the generated one read address to the storage device.
To attain the above object, the present invention provides a digital signal processing method comprising a storing step of storing plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing in a storage device, a counting step of updating a count value of a counter every sampling period and generating the updated count value as a basic address, and an input or output step of performing an input and output operation every sampling period, the input and output operation comprising generating plural kinds of offset addresses corresponding, respectively, to the plural kinds of signal processing and not overlapping with each other, generating at least one write address or read address for the sampled data for each of the plural kinds of signal processing by modifying the basic address by at least one of the offset addresses corresponding to each of the plural kinds of signal processing, and delivering the generated at least one write address or read address to the storage device.
REFERENCES:
patent: 5210701 (1993-05-01), Hana et al.
patent: 6101583 (2000-08-01), Suzuki
patent: 6201245 (2001-03-01), Schrader
Matsushita Ritsuo
Muraki Yasuyuki
Yamamoto Yusuke
Farooq Mohammad O.
Gaffin Jeffrey
Yamaha Corporation
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