Digital signal processor

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3642318, 3642641, 3642286, 3642443, 3642551, 3642448, G06F 938, G06F 926

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active

050459937

ABSTRACT:
A digital signal processor of a simple circuit configuration capable of implementing arithmetic processes and interruption processes efficiently in a reduced number of steps at a high processing speed. The digital signal processor comprises instruction execution pipeline stages including a stage in which data is read from a data memory and the data is applied to an arithmetic unit; an arithmetic unit for the execution stage, including a barrel shifter, a multiplier and an arithmetic and logic unit, a normalizing barrel shifter, a round-off/accumulation adder, internal data memories and a DMA transfer bus for a write/accumulation stage, an address generating unit capable of parallel and two-dimensional generation of two inputs one output data memory addresses and a DMA control unit for controlling the two-dimensional data transfer through a DMA bus between the internal data memories and an external data memory for an instruction execution stage.

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Jonathan Allen, "Computer Architecture for Signal Processing", Apr. 4, 1978, pp. 624-633.
Louis Schirm IV, "Packing a Signal Processor onto a Single Digital Board", Dec. 20, 1979, pp. 109-115.
Takao Kaneko et al., "A 50NS Floating-Point Signal Processor VLSI", IEEE 1986, pp. 401-404.

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