Digital signal processor

Details Digital signal processor Digital signal processor

1999-06-18

2002-08-06

Pan, Daniel H. (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S221000, C712S222000, C712S223000, C712S237000, C712S035000, C708S490000, C708S508000

Reexamination Certificate

active

06430681

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital signal processor with an improved arithmetic processing performance.
2. Description of the Background Art
In devices such as digital audio devices, a variety of digital filters are used for signal filtering processing. Such digital filters generally comprise a digital signal processor (DSP) including a plurality of registers combined with an adder and a multiplier.
FIG. 8
is a circuit diagram showing a typical configuration of a digital filter.
The digital filter comprises an adder
1
, a first, a second, and a third multiplier
2
a
-
2
c
, and a first and a second latch
3
a
,
3
b
. The first multiplier
2
a
multiplies an input digital data item X(a) by a first filter factor h(a). The first latch
3
a
latches and retains input digital data X(n) for one data period. The second multiplier
2
b
multiplies the immediately preceding digital data X(n−1) retained in the first latch
3
a
by the second filter factor hb. The second latch
3
b
holds digital data Y(n) output from the adder
1
, and retains this data for one data period. The third multiplier
2
c
multiplies the immediately preceding digital data Y(n−1) retained in the second latch
3
b
by a third filter fact or hc. The adder
1
adds up the multiplication results output from the first to third multipliers
2
a
-
2
c
, and outputs the sum as new digital data Y(n). Accordingly, with respect to the input digital data X(n), the output digital data Y(n) is generated according to the following equation:
Y
(
n
)=
X
(
n
)·
ha+X
(
n
−1)·
hb+Y
(
n
−1)·
hc.
FIG. 9
is a block diagram illustrating a typical configuration of a digital signal processor.
The digital signal processor comprises an arithmetic circuit
11
, a RAM
12
, a memory control circuit
13
, a ROM
14
, and an instruction decoder
15
. The arithmetic circuit
11
includes an adder and a multiplier. In response to instructions from the instruction decoder
15
, the arithmetic circuit
11
performs various arithmetic processing on the input digital data X(n), intermediate data, and various factor data stored in the RAM
12
, and then outputs the final calculation result as the digital data Y(n). The RAM
12
temporarily stores the digital data X(n) input into the arithmetic circuit
11
, the digital data Y(n) output from the arithmetic circuit
11
, and the intermediate data generated during the calculation processes in the arithmetic circuit
11
. The RAM
12
also stores the various factor data. The memory control circuit
13
, in response to instructions from the instruction decoder
15
, reads out necessary data from the RAM
12
in accordance with the arithmetic operations of the arithmetic circuit
11
, and supplies the data to the arithmetic circuit
11
.
The ROM
14
stores a program that instructs the calculation procedures for the arithmetic circuit
11
. The ROM
14
reads out each of the instructions in a predetermined sequence in accordance with a clock having a constant cycle, and supplies the instructions to the instruction decoder
15
. The instruction decoder
15
interprets the instructions input from the ROM
14
, and controls arithmetic operations of the arithmetic circuit
11
. The instruction decoder
15
also controls read and write operations of the memory control circuit
13
.
When putting the digital filter shown in
FIG. 8
into actual practice, the ROM
14
contains, for example, a program executing the following arithmetic steps. In the following example, it is assumed that the immediately preceding data items X(n−1) and Y(n−1), and the filter factors ha, hb, and hc are stored in the RAM
12
.
1) Read out the filter factor ha from the RAM
12
. Multiply the input data X(n) by the filter factor ha, and store the product in the RAM
12
. At the same time, store the data X(n) in the RAM
12
.
2) Read out the immediately preceding data X(n−1) and the filter factor hb from the RAM
12
, and multiply these items by each other. Store the product in the RAM
12
.
3) Read out from the RAM
12
the product stored in step 1) and the product stored in step 2). Add these products, and store the sum in the RAM
12
.
4) Read out the immediately preceding data Y(n−1) and the filter factor hc from the RAM
12
, and multiply these items by each other. Store the product in the RAM
12
.
5) Read out from the RAM
12
the sum stored in step 3) and the product stored in step 4), and add them together. Output the newly obtained sum as the data Y(n). At the same time, store the data Y(n) in the RAM
12
.
In the above arithmetic operation, only one multiplication or addition processing is executed in each step. It is therefore not necessary to provide a plurality of multipliers or adders in the arithmetic circuit
11
. The circuit configuration can therefore be simplified.
The control program stored in the ROM
14
generally comprises branch commands for instructing the calculation sequence and the sequence for reading out each data (including factors), and arithmetic commands for executing the actual calculations such as multiplication and addition. These branch commands and arithmetic commands are stored in the ROM
14
in an intermingled state in a predetermined sequence. These instructions are read out from the ROM
14
in a predetermined sequence and supplied to the instruction decoder
15
. This means that, when the signal processing is more complex or has more arithmetic steps, the size of the control program becomes larger and the time required for the signal processing grows long.
SUMMARY OF THE INVENTION
In light of the above, an object of the present invention is to prevent the signal processing time from becoming longer when the number of arithmetic steps are increased.
According to the present invention created for solving the above problem, there is provided a digital signal processor performing a plurality of stages of arithmetic processing on first digital data to generate second digital data, comprising a first memory for storing branch commands controlling a sequential flow of said plurality of stages of arithmetic processing; a second memory for storing arithmetic commands controlling operation in each of said plurality of stages of arithmetic processing; a first memory control circuit for designating addresses in each of said first and said second memories in a fixed sequence and for reading out said branch commands and said arithmetic commands; and an arithmetic circuit for performing arithmetic processing on said first digital data according to said branch commands and said arithmetic commands read out from said first and said second memories; wherein said first memory control circuit jumps to a predetermined address within the addresses of said second memory in response to said branch commands.
According to the present invention, branch commands and arithmetic commands can be processed simultaneously, permitting execution of increased number of steps in a short period of time.
The present digital signal processor can preferably be used as a digital filter for a digital audio device.


REFERENCES:
patent: 4245327 (1981-01-01), Moriya et al.
patent: 5450553 (1995-09-01), Kitagaki et al.

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