Digital signal processing system utilizing relatively slower spe

Details Digital signal processing system utilizing relatively slower spe Digital signal processing system utilizing relatively slower spe

1993-09-21

1996-08-06

Heckler, Thomas M.

Boots, shoes, and leggings

395405, 39542101, 364DIG1, G06F 1200

Patent

active

055443516

ABSTRACT:
A digital signal processing system of the present invention enables a high speed digital signal processor (DSP) to run at full speed, despite accessing data stored in a number of relatively slower memory modules. The system demultiplexes a high speed address bus into parallel lower-speed address buses for each of several relatively slower memory modules. The use of address demultiplexing allows for use of low speed memory, while providing for the full capabilities of a high speed DSP. The data from the memory modules is multiplexed into a single high-speed data bus, and read by the DSP. A write operation is also possible by the addition of an additional demultiplexer in the data bus.

REFERENCES:
patent: 4415991 (1983-11-01), Chu et al.

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