Digital signal processing method and system implementing pipelin

Details Digital signal processing method and system implementing pipelin Digital signal processing method and system implementing pipelin

1995-12-29

1998-01-20

Pan, Daniel H.

Boots, shoes, and leggings

395384, 39580009, 395393, 364DIG1, 364DIG2, G06F 938, G06F 934, G06F 942

Patent

active

057109141

ABSTRACT:
A digital signal processing system and method for executing instructions with decode, read, execute, and write pipeline cycles. In the decode cycle, control signals are generated which determine addresses which in turn determine memory locations from which data are to be read and to which processed data are to be written. The system includes a program control unit for processing a sequence of instructions and controlling system operation, a memory, a data processing unit, and a dedicated bus for writing processed data from the data processing unit to the memory. By using a dedicated write bus, the system avoids bus contention in a five stage pipeline operation involving fetch, decode, read, execute, and write operations. A post shift unit connected along the write bus shifts data values that have been output from the data processing unit before they are written to the memory. The system also executes instructions in a pipelined manner, in which addresses for reads from a memory are asserted on an address bus in one pipeline cycle and addresses for writes to the memory are asserted on the address bus in a different pipeline cycle.

REFERENCES:
patent: 4454578 (1984-06-01), Matsumoto
patent: 4598359 (1986-07-01), Boothroyd et al.
patent: 4626989 (1986-12-01), Torii
patent: 5333284 (1994-07-01), Nugent
patent: 5438668 (1995-08-01), Coon et al.

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